interrupts.hh revision 9294
14120Sgblack@eecs.umich.edu/* 28839Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38839Sandreas.hansson@arm.com * All rights reserved 48839Sandreas.hansson@arm.com * 58839Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68839Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78839Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88839Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98839Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108839Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118839Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128839Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138839Sandreas.hansson@arm.com * 144120Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 154120Sgblack@eecs.umich.edu * All rights reserved. 164120Sgblack@eecs.umich.edu * 177087Snate@binkert.org * The license below extends only to copyright in the software and shall 187087Snate@binkert.org * not be construed as granting a license to any other intellectual 197087Snate@binkert.org * property including but not limited to intellectual property relating 207087Snate@binkert.org * to a hardware implementation of the functionality of the software 217087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 227087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 237087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 247087Snate@binkert.org * modified or unmodified, in source code or in binary form. 254120Sgblack@eecs.umich.edu * 267087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 277087Snate@binkert.org * modification, are permitted provided that the following conditions are 287087Snate@binkert.org * met: redistributions of source code must retain the above copyright 297087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 307087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 317087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 327087Snate@binkert.org * documentation and/or other materials provided with the distribution; 337087Snate@binkert.org * neither the name of the copyright holders nor the names of its 344120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 357087Snate@binkert.org * this software without specific prior written permission. 364120Sgblack@eecs.umich.edu * 374120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 384120Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 394120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 404120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 414120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 424120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 434120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 444120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 454120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 464120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 474120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 484120Sgblack@eecs.umich.edu * 494120Sgblack@eecs.umich.edu * Authors: Gabe Black 508839Sandreas.hansson@arm.com * Andreas Hansson 514120Sgblack@eecs.umich.edu */ 524120Sgblack@eecs.umich.edu 534120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_INTERRUPTS_HH__ 544120Sgblack@eecs.umich.edu#define __ARCH_X86_INTERRUPTS_HH__ 554120Sgblack@eecs.umich.edu 568229Snate@binkert.org#include "arch/x86/regs/apic.hh" 575086Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 585655Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 595654Sgblack@eecs.umich.edu#include "base/bitfield.hh" 605086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 618229Snate@binkert.org#include "dev/x86/intdev.hh" 625648Sgblack@eecs.umich.edu#include "dev/io_device.hh" 635647Sgblack@eecs.umich.edu#include "params/X86LocalApic.hh" 645647Sgblack@eecs.umich.edu#include "sim/eventq.hh" 655647Sgblack@eecs.umich.edu 665647Sgblack@eecs.umich.educlass ThreadContext; 675810Sgblack@eecs.umich.educlass BaseCPU; 684120Sgblack@eecs.umich.edu 695704Snate@binkert.orgnamespace X86ISA { 705086Sgblack@eecs.umich.edu 715651Sgblack@eecs.umich.educlass Interrupts : public BasicPioDevice, IntDev 725086Sgblack@eecs.umich.edu{ 735647Sgblack@eecs.umich.edu protected: 745654Sgblack@eecs.umich.edu // Storage for the APIC registers 755647Sgblack@eecs.umich.edu uint32_t regs[NUM_APIC_REGS]; 765654Sgblack@eecs.umich.edu 775691Sgblack@eecs.umich.edu BitUnion32(LVTEntry) 785691Sgblack@eecs.umich.edu Bitfield<7, 0> vector; 795691Sgblack@eecs.umich.edu Bitfield<10, 8> deliveryMode; 805691Sgblack@eecs.umich.edu Bitfield<12> status; 815691Sgblack@eecs.umich.edu Bitfield<13> polarity; 825691Sgblack@eecs.umich.edu Bitfield<14> remoteIRR; 835691Sgblack@eecs.umich.edu Bitfield<15> trigger; 845691Sgblack@eecs.umich.edu Bitfield<16> masked; 855691Sgblack@eecs.umich.edu Bitfield<17> periodic; 865691Sgblack@eecs.umich.edu EndBitUnion(LVTEntry) 875691Sgblack@eecs.umich.edu 885654Sgblack@eecs.umich.edu /* 895654Sgblack@eecs.umich.edu * Timing related stuff. 905654Sgblack@eecs.umich.edu */ 915648Sgblack@eecs.umich.edu Tick latency; 925647Sgblack@eecs.umich.edu 935647Sgblack@eecs.umich.edu class ApicTimerEvent : public Event 945647Sgblack@eecs.umich.edu { 955691Sgblack@eecs.umich.edu private: 965691Sgblack@eecs.umich.edu Interrupts *localApic; 975647Sgblack@eecs.umich.edu public: 985691Sgblack@eecs.umich.edu ApicTimerEvent(Interrupts *_localApic) : 995691Sgblack@eecs.umich.edu Event(), localApic(_localApic) 1005647Sgblack@eecs.umich.edu {} 1015647Sgblack@eecs.umich.edu 1025647Sgblack@eecs.umich.edu void process() 1035647Sgblack@eecs.umich.edu { 1045691Sgblack@eecs.umich.edu assert(localApic); 1055691Sgblack@eecs.umich.edu if (localApic->triggerTimerInterrupt()) { 1065691Sgblack@eecs.umich.edu localApic->setReg(APIC_INITIAL_COUNT, 1075691Sgblack@eecs.umich.edu localApic->readReg(APIC_INITIAL_COUNT)); 1085691Sgblack@eecs.umich.edu } 1095647Sgblack@eecs.umich.edu } 1105647Sgblack@eecs.umich.edu }; 1115647Sgblack@eecs.umich.edu 1125647Sgblack@eecs.umich.edu ApicTimerEvent apicTimerEvent; 1135647Sgblack@eecs.umich.edu 1145654Sgblack@eecs.umich.edu /* 1155655Sgblack@eecs.umich.edu * A set of variables to keep track of interrupts that don't go through 1165655Sgblack@eecs.umich.edu * the IRR. 1175655Sgblack@eecs.umich.edu */ 1185655Sgblack@eecs.umich.edu bool pendingSmi; 1195691Sgblack@eecs.umich.edu uint8_t smiVector; 1205655Sgblack@eecs.umich.edu bool pendingNmi; 1215691Sgblack@eecs.umich.edu uint8_t nmiVector; 1225655Sgblack@eecs.umich.edu bool pendingExtInt; 1235691Sgblack@eecs.umich.edu uint8_t extIntVector; 1245655Sgblack@eecs.umich.edu bool pendingInit; 1255691Sgblack@eecs.umich.edu uint8_t initVector; 1266050Sgblack@eecs.umich.edu bool pendingStartup; 1276050Sgblack@eecs.umich.edu uint8_t startupVector; 1286066Sgblack@eecs.umich.edu bool startedUp; 1295655Sgblack@eecs.umich.edu 1305655Sgblack@eecs.umich.edu // This is a quick check whether any of the above (except ExtInt) are set. 1315655Sgblack@eecs.umich.edu bool pendingUnmaskableInt; 1325655Sgblack@eecs.umich.edu 1336069Sgblack@eecs.umich.edu // A count of how many IPIs are in flight. 1346069Sgblack@eecs.umich.edu int pendingIPIs; 1356069Sgblack@eecs.umich.edu 1365655Sgblack@eecs.umich.edu /* 1375654Sgblack@eecs.umich.edu * IRR and ISR maintenance. 1385654Sgblack@eecs.umich.edu */ 1395654Sgblack@eecs.umich.edu uint8_t IRRV; 1405654Sgblack@eecs.umich.edu uint8_t ISRV; 1415654Sgblack@eecs.umich.edu 1425654Sgblack@eecs.umich.edu int 1435654Sgblack@eecs.umich.edu findRegArrayMSB(ApicRegIndex base) 1445654Sgblack@eecs.umich.edu { 1455654Sgblack@eecs.umich.edu int offset = 7; 1465654Sgblack@eecs.umich.edu do { 1475654Sgblack@eecs.umich.edu if (regs[base + offset] != 0) { 1485654Sgblack@eecs.umich.edu return offset * 32 + findMsbSet(regs[base + offset]); 1495654Sgblack@eecs.umich.edu } 1505654Sgblack@eecs.umich.edu } while (offset--); 1515654Sgblack@eecs.umich.edu return 0; 1525654Sgblack@eecs.umich.edu } 1535654Sgblack@eecs.umich.edu 1545654Sgblack@eecs.umich.edu void 1555654Sgblack@eecs.umich.edu updateIRRV() 1565654Sgblack@eecs.umich.edu { 1575654Sgblack@eecs.umich.edu IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE); 1585654Sgblack@eecs.umich.edu } 1595654Sgblack@eecs.umich.edu 1605654Sgblack@eecs.umich.edu void 1615654Sgblack@eecs.umich.edu updateISRV() 1625654Sgblack@eecs.umich.edu { 1635654Sgblack@eecs.umich.edu ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE); 1645654Sgblack@eecs.umich.edu } 1655654Sgblack@eecs.umich.edu 1665654Sgblack@eecs.umich.edu void 1675654Sgblack@eecs.umich.edu setRegArrayBit(ApicRegIndex base, uint8_t vector) 1685654Sgblack@eecs.umich.edu { 1696101Sgblack@eecs.umich.edu regs[base + (vector / 32)] |= (1 << (vector % 32)); 1705654Sgblack@eecs.umich.edu } 1715654Sgblack@eecs.umich.edu 1725654Sgblack@eecs.umich.edu void 1735654Sgblack@eecs.umich.edu clearRegArrayBit(ApicRegIndex base, uint8_t vector) 1745654Sgblack@eecs.umich.edu { 1756101Sgblack@eecs.umich.edu regs[base + (vector / 32)] &= ~(1 << (vector % 32)); 1765654Sgblack@eecs.umich.edu } 1775654Sgblack@eecs.umich.edu 1785654Sgblack@eecs.umich.edu bool 1795654Sgblack@eecs.umich.edu getRegArrayBit(ApicRegIndex base, uint8_t vector) 1805654Sgblack@eecs.umich.edu { 1816101Sgblack@eecs.umich.edu return bits(regs[base + (vector / 32)], vector % 5); 1825654Sgblack@eecs.umich.edu } 1835654Sgblack@eecs.umich.edu 1845691Sgblack@eecs.umich.edu void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level); 1855691Sgblack@eecs.umich.edu 1865810Sgblack@eecs.umich.edu BaseCPU *cpu; 1875810Sgblack@eecs.umich.edu 1886136Sgblack@eecs.umich.edu int initialApicId; 1896136Sgblack@eecs.umich.edu 1908851Sandreas.hansson@arm.com // Port for receiving interrupts 1918922Swilliam.wang@arm.com IntSlavePort intSlavePort; 1928851Sandreas.hansson@arm.com 1935086Sgblack@eecs.umich.edu public: 1948742Sgblack@eecs.umich.edu 1958746Sgblack@eecs.umich.edu int getInitialApicId() { return initialApicId; } 1968746Sgblack@eecs.umich.edu 1975654Sgblack@eecs.umich.edu /* 1985654Sgblack@eecs.umich.edu * Params stuff. 1995654Sgblack@eecs.umich.edu */ 2005647Sgblack@eecs.umich.edu typedef X86LocalApicParams Params; 2015647Sgblack@eecs.umich.edu 2026041Sgblack@eecs.umich.edu void setCPU(BaseCPU * newCPU); 2035810Sgblack@eecs.umich.edu 2045810Sgblack@eecs.umich.edu void 2055704Snate@binkert.org setClock(Tick newClock) 2065648Sgblack@eecs.umich.edu { 2075648Sgblack@eecs.umich.edu clock = newClock; 2085648Sgblack@eecs.umich.edu } 2095648Sgblack@eecs.umich.edu 2105647Sgblack@eecs.umich.edu const Params * 2115647Sgblack@eecs.umich.edu params() const 2125086Sgblack@eecs.umich.edu { 2135647Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 2145647Sgblack@eecs.umich.edu } 2155647Sgblack@eecs.umich.edu 2165654Sgblack@eecs.umich.edu /* 2176137Sgblack@eecs.umich.edu * Initialize this object by registering it with the IO APIC. 2186137Sgblack@eecs.umich.edu */ 2196137Sgblack@eecs.umich.edu void init(); 2206137Sgblack@eecs.umich.edu 2216137Sgblack@eecs.umich.edu /* 2225654Sgblack@eecs.umich.edu * Functions to interact with the interrupt port from IntDev. 2235654Sgblack@eecs.umich.edu */ 2245648Sgblack@eecs.umich.edu Tick read(PacketPtr pkt); 2255648Sgblack@eecs.umich.edu Tick write(PacketPtr pkt); 2265651Sgblack@eecs.umich.edu Tick recvMessage(PacketPtr pkt); 2276064Sgblack@eecs.umich.edu Tick recvResponse(PacketPtr pkt); 2285647Sgblack@eecs.umich.edu 2295691Sgblack@eecs.umich.edu bool 2305691Sgblack@eecs.umich.edu triggerTimerInterrupt() 2315691Sgblack@eecs.umich.edu { 2325691Sgblack@eecs.umich.edu LVTEntry entry = regs[APIC_LVT_TIMER]; 2335691Sgblack@eecs.umich.edu if (!entry.masked) 2345691Sgblack@eecs.umich.edu requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger); 2355691Sgblack@eecs.umich.edu return entry.periodic; 2365691Sgblack@eecs.umich.edu } 2375691Sgblack@eecs.umich.edu 2389090Sandreas.hansson@arm.com AddrRangeList getAddrRanges() const; 2399090Sandreas.hansson@arm.com AddrRangeList getIntAddrRange() const; 2405651Sgblack@eecs.umich.edu 2419294Sandreas.hansson@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 2429294Sandreas.hansson@arm.com PortID idx = InvalidPortID) 2435654Sgblack@eecs.umich.edu { 2448839Sandreas.hansson@arm.com if (if_name == "int_master") { 2458922Swilliam.wang@arm.com return intMasterPort; 2468839Sandreas.hansson@arm.com } 2478922Swilliam.wang@arm.com return BasicPioDevice::getMasterPort(if_name, idx); 2488922Swilliam.wang@arm.com } 2498922Swilliam.wang@arm.com 2509294Sandreas.hansson@arm.com BaseSlavePort &getSlavePort(const std::string &if_name, 2519294Sandreas.hansson@arm.com PortID idx = InvalidPortID) 2528922Swilliam.wang@arm.com { 2538922Swilliam.wang@arm.com if (if_name == "int_slave") { 2548922Swilliam.wang@arm.com return intSlavePort; 2558922Swilliam.wang@arm.com } 2568922Swilliam.wang@arm.com return BasicPioDevice::getSlavePort(if_name, idx); 2575654Sgblack@eecs.umich.edu } 2585654Sgblack@eecs.umich.edu 2595654Sgblack@eecs.umich.edu /* 2605654Sgblack@eecs.umich.edu * Functions to access and manipulate the APIC's registers. 2615654Sgblack@eecs.umich.edu */ 2625654Sgblack@eecs.umich.edu 2635648Sgblack@eecs.umich.edu uint32_t readReg(ApicRegIndex miscReg); 2645648Sgblack@eecs.umich.edu void setReg(ApicRegIndex reg, uint32_t val); 2655704Snate@binkert.org void 2665704Snate@binkert.org setRegNoEffect(ApicRegIndex reg, uint32_t val) 2675647Sgblack@eecs.umich.edu { 2685648Sgblack@eecs.umich.edu regs[reg] = val; 2695648Sgblack@eecs.umich.edu } 2705648Sgblack@eecs.umich.edu 2715654Sgblack@eecs.umich.edu /* 2725654Sgblack@eecs.umich.edu * Constructor. 2735654Sgblack@eecs.umich.edu */ 2745654Sgblack@eecs.umich.edu 2756041Sgblack@eecs.umich.edu Interrupts(Params * p); 2765086Sgblack@eecs.umich.edu 2775654Sgblack@eecs.umich.edu /* 2785654Sgblack@eecs.umich.edu * Functions for retrieving interrupts for the CPU to handle. 2795654Sgblack@eecs.umich.edu */ 2805651Sgblack@eecs.umich.edu 2815704Snate@binkert.org bool checkInterrupts(ThreadContext *tc) const; 2825704Snate@binkert.org Fault getInterrupt(ThreadContext *tc); 2835704Snate@binkert.org void updateIntrInfo(ThreadContext *tc); 2845086Sgblack@eecs.umich.edu 2855654Sgblack@eecs.umich.edu /* 2865654Sgblack@eecs.umich.edu * Serialization. 2875654Sgblack@eecs.umich.edu */ 2885086Sgblack@eecs.umich.edu 2897902Shestness@cs.utexas.edu virtual void serialize(std::ostream &os); 2907902Shestness@cs.utexas.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 2915654Sgblack@eecs.umich.edu 2925654Sgblack@eecs.umich.edu /* 2935654Sgblack@eecs.umich.edu * Old functions needed for compatability but which will be phased out 2945654Sgblack@eecs.umich.edu * eventually. 2955654Sgblack@eecs.umich.edu */ 2965704Snate@binkert.org void 2975704Snate@binkert.org post(int int_num, int index) 2985654Sgblack@eecs.umich.edu { 2995654Sgblack@eecs.umich.edu panic("Interrupts::post unimplemented!\n"); 3005654Sgblack@eecs.umich.edu } 3015654Sgblack@eecs.umich.edu 3025704Snate@binkert.org void 3035704Snate@binkert.org clear(int int_num, int index) 3045654Sgblack@eecs.umich.edu { 3055654Sgblack@eecs.umich.edu panic("Interrupts::clear unimplemented!\n"); 3065654Sgblack@eecs.umich.edu } 3075654Sgblack@eecs.umich.edu 3085704Snate@binkert.org void 3095704Snate@binkert.org clearAll() 3105654Sgblack@eecs.umich.edu { 3115704Snate@binkert.org panic("Interrupts::clearAll unimplemented!\n"); 3125654Sgblack@eecs.umich.edu } 3135086Sgblack@eecs.umich.edu}; 3145086Sgblack@eecs.umich.edu 3155704Snate@binkert.org} // namespace X86ISA 3164120Sgblack@eecs.umich.edu 3174120Sgblack@eecs.umich.edu#endif // __ARCH_X86_INTERRUPTS_HH__ 318