interrupts.hh revision 6069
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IN NO EVENT SHALL THE COPYRIGHT 474120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544120Sgblack@eecs.umich.edu * 554120Sgblack@eecs.umich.edu * Authors: Gabe Black 564120Sgblack@eecs.umich.edu */ 574120Sgblack@eecs.umich.edu 584120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_INTERRUPTS_HH__ 594120Sgblack@eecs.umich.edu#define __ARCH_X86_INTERRUPTS_HH__ 604120Sgblack@eecs.umich.edu 615647Sgblack@eecs.umich.edu#include "arch/x86/apicregs.hh" 625086Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 635655Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 645654Sgblack@eecs.umich.edu#include "base/bitfield.hh" 655086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 665648Sgblack@eecs.umich.edu#include "dev/io_device.hh" 675651Sgblack@eecs.umich.edu#include "dev/x86/intdev.hh" 685647Sgblack@eecs.umich.edu#include "params/X86LocalApic.hh" 695647Sgblack@eecs.umich.edu#include "sim/eventq.hh" 705647Sgblack@eecs.umich.edu 715647Sgblack@eecs.umich.educlass ThreadContext; 725810Sgblack@eecs.umich.educlass BaseCPU; 734120Sgblack@eecs.umich.edu 745704Snate@binkert.orgnamespace X86ISA { 755086Sgblack@eecs.umich.edu 765651Sgblack@eecs.umich.educlass Interrupts : public BasicPioDevice, IntDev 775086Sgblack@eecs.umich.edu{ 785647Sgblack@eecs.umich.edu protected: 795654Sgblack@eecs.umich.edu // Storage for the APIC registers 805647Sgblack@eecs.umich.edu uint32_t regs[NUM_APIC_REGS]; 815654Sgblack@eecs.umich.edu 825691Sgblack@eecs.umich.edu BitUnion32(LVTEntry) 835691Sgblack@eecs.umich.edu Bitfield<7, 0> vector; 845691Sgblack@eecs.umich.edu Bitfield<10, 8> deliveryMode; 855691Sgblack@eecs.umich.edu Bitfield<12> status; 865691Sgblack@eecs.umich.edu Bitfield<13> polarity; 875691Sgblack@eecs.umich.edu Bitfield<14> remoteIRR; 885691Sgblack@eecs.umich.edu Bitfield<15> trigger; 895691Sgblack@eecs.umich.edu Bitfield<16> masked; 905691Sgblack@eecs.umich.edu Bitfield<17> periodic; 915691Sgblack@eecs.umich.edu EndBitUnion(LVTEntry) 925691Sgblack@eecs.umich.edu 935654Sgblack@eecs.umich.edu /* 945654Sgblack@eecs.umich.edu * Timing related stuff. 955654Sgblack@eecs.umich.edu */ 965648Sgblack@eecs.umich.edu Tick latency; 975648Sgblack@eecs.umich.edu Tick clock; 985647Sgblack@eecs.umich.edu 995647Sgblack@eecs.umich.edu class ApicTimerEvent : public Event 1005647Sgblack@eecs.umich.edu { 1015691Sgblack@eecs.umich.edu private: 1025691Sgblack@eecs.umich.edu Interrupts *localApic; 1035647Sgblack@eecs.umich.edu public: 1045691Sgblack@eecs.umich.edu ApicTimerEvent(Interrupts *_localApic) : 1055691Sgblack@eecs.umich.edu Event(), localApic(_localApic) 1065647Sgblack@eecs.umich.edu {} 1075647Sgblack@eecs.umich.edu 1085647Sgblack@eecs.umich.edu void process() 1095647Sgblack@eecs.umich.edu { 1105691Sgblack@eecs.umich.edu assert(localApic); 1115691Sgblack@eecs.umich.edu if (localApic->triggerTimerInterrupt()) { 1125691Sgblack@eecs.umich.edu localApic->setReg(APIC_INITIAL_COUNT, 1135691Sgblack@eecs.umich.edu localApic->readReg(APIC_INITIAL_COUNT)); 1145691Sgblack@eecs.umich.edu } 1155647Sgblack@eecs.umich.edu } 1165647Sgblack@eecs.umich.edu }; 1175647Sgblack@eecs.umich.edu 1185647Sgblack@eecs.umich.edu ApicTimerEvent apicTimerEvent; 1195647Sgblack@eecs.umich.edu 1205654Sgblack@eecs.umich.edu /* 1215655Sgblack@eecs.umich.edu * A set of variables to keep track of interrupts that don't go through 1225655Sgblack@eecs.umich.edu * the IRR. 1235655Sgblack@eecs.umich.edu */ 1245655Sgblack@eecs.umich.edu bool pendingSmi; 1255691Sgblack@eecs.umich.edu uint8_t smiVector; 1265655Sgblack@eecs.umich.edu bool pendingNmi; 1275691Sgblack@eecs.umich.edu uint8_t nmiVector; 1285655Sgblack@eecs.umich.edu bool pendingExtInt; 1295691Sgblack@eecs.umich.edu uint8_t extIntVector; 1305655Sgblack@eecs.umich.edu bool pendingInit; 1315691Sgblack@eecs.umich.edu uint8_t initVector; 1326050Sgblack@eecs.umich.edu bool pendingStartup; 1336050Sgblack@eecs.umich.edu uint8_t startupVector; 1346066Sgblack@eecs.umich.edu bool startedUp; 1355655Sgblack@eecs.umich.edu 1365655Sgblack@eecs.umich.edu // This is a quick check whether any of the above (except ExtInt) are set. 1375655Sgblack@eecs.umich.edu bool pendingUnmaskableInt; 1385655Sgblack@eecs.umich.edu 1396069Sgblack@eecs.umich.edu // A count of how many IPIs are in flight. 1406069Sgblack@eecs.umich.edu int pendingIPIs; 1416069Sgblack@eecs.umich.edu 1425655Sgblack@eecs.umich.edu /* 1435654Sgblack@eecs.umich.edu * IRR and ISR maintenance. 1445654Sgblack@eecs.umich.edu */ 1455654Sgblack@eecs.umich.edu uint8_t IRRV; 1465654Sgblack@eecs.umich.edu uint8_t ISRV; 1475654Sgblack@eecs.umich.edu 1485654Sgblack@eecs.umich.edu int 1495654Sgblack@eecs.umich.edu findRegArrayMSB(ApicRegIndex base) 1505654Sgblack@eecs.umich.edu { 1515654Sgblack@eecs.umich.edu int offset = 7; 1525654Sgblack@eecs.umich.edu do { 1535654Sgblack@eecs.umich.edu if (regs[base + offset] != 0) { 1545654Sgblack@eecs.umich.edu return offset * 32 + findMsbSet(regs[base + offset]); 1555654Sgblack@eecs.umich.edu } 1565654Sgblack@eecs.umich.edu } while (offset--); 1575654Sgblack@eecs.umich.edu return 0; 1585654Sgblack@eecs.umich.edu } 1595654Sgblack@eecs.umich.edu 1605654Sgblack@eecs.umich.edu void 1615654Sgblack@eecs.umich.edu updateIRRV() 1625654Sgblack@eecs.umich.edu { 1635654Sgblack@eecs.umich.edu IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE); 1645654Sgblack@eecs.umich.edu } 1655654Sgblack@eecs.umich.edu 1665654Sgblack@eecs.umich.edu void 1675654Sgblack@eecs.umich.edu updateISRV() 1685654Sgblack@eecs.umich.edu { 1695654Sgblack@eecs.umich.edu ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE); 1705654Sgblack@eecs.umich.edu } 1715654Sgblack@eecs.umich.edu 1725654Sgblack@eecs.umich.edu void 1735654Sgblack@eecs.umich.edu setRegArrayBit(ApicRegIndex base, uint8_t vector) 1745654Sgblack@eecs.umich.edu { 1755654Sgblack@eecs.umich.edu regs[base + (vector % 32)] |= (1 << (vector >> 5)); 1765654Sgblack@eecs.umich.edu } 1775654Sgblack@eecs.umich.edu 1785654Sgblack@eecs.umich.edu void 1795654Sgblack@eecs.umich.edu clearRegArrayBit(ApicRegIndex base, uint8_t vector) 1805654Sgblack@eecs.umich.edu { 1815654Sgblack@eecs.umich.edu regs[base + (vector % 32)] &= ~(1 << (vector >> 5)); 1825654Sgblack@eecs.umich.edu } 1835654Sgblack@eecs.umich.edu 1845654Sgblack@eecs.umich.edu bool 1855654Sgblack@eecs.umich.edu getRegArrayBit(ApicRegIndex base, uint8_t vector) 1865654Sgblack@eecs.umich.edu { 1875654Sgblack@eecs.umich.edu return bits(regs[base + (vector % 32)], vector >> 5); 1885654Sgblack@eecs.umich.edu } 1895654Sgblack@eecs.umich.edu 1905691Sgblack@eecs.umich.edu void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level); 1915691Sgblack@eecs.umich.edu 1925810Sgblack@eecs.umich.edu BaseCPU *cpu; 1935810Sgblack@eecs.umich.edu 1945086Sgblack@eecs.umich.edu public: 1955654Sgblack@eecs.umich.edu /* 1965654Sgblack@eecs.umich.edu * Params stuff. 1975654Sgblack@eecs.umich.edu */ 1985647Sgblack@eecs.umich.edu typedef X86LocalApicParams Params; 1995647Sgblack@eecs.umich.edu 2006041Sgblack@eecs.umich.edu void setCPU(BaseCPU * newCPU); 2015810Sgblack@eecs.umich.edu 2025810Sgblack@eecs.umich.edu void 2035704Snate@binkert.org setClock(Tick newClock) 2045648Sgblack@eecs.umich.edu { 2055648Sgblack@eecs.umich.edu clock = newClock; 2065648Sgblack@eecs.umich.edu } 2075648Sgblack@eecs.umich.edu 2085647Sgblack@eecs.umich.edu const Params * 2095647Sgblack@eecs.umich.edu params() const 2105086Sgblack@eecs.umich.edu { 2115647Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 2125647Sgblack@eecs.umich.edu } 2135647Sgblack@eecs.umich.edu 2145654Sgblack@eecs.umich.edu /* 2155654Sgblack@eecs.umich.edu * Functions to interact with the interrupt port from IntDev. 2165654Sgblack@eecs.umich.edu */ 2175648Sgblack@eecs.umich.edu Tick read(PacketPtr pkt); 2185648Sgblack@eecs.umich.edu Tick write(PacketPtr pkt); 2195651Sgblack@eecs.umich.edu Tick recvMessage(PacketPtr pkt); 2206064Sgblack@eecs.umich.edu Tick recvResponse(PacketPtr pkt); 2215647Sgblack@eecs.umich.edu 2225691Sgblack@eecs.umich.edu bool 2235691Sgblack@eecs.umich.edu triggerTimerInterrupt() 2245691Sgblack@eecs.umich.edu { 2255691Sgblack@eecs.umich.edu LVTEntry entry = regs[APIC_LVT_TIMER]; 2265691Sgblack@eecs.umich.edu if (!entry.masked) 2275691Sgblack@eecs.umich.edu requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger); 2285691Sgblack@eecs.umich.edu return entry.periodic; 2295691Sgblack@eecs.umich.edu } 2305691Sgblack@eecs.umich.edu 2316041Sgblack@eecs.umich.edu void addressRanges(AddrRangeList &range_list); 2326041Sgblack@eecs.umich.edu void getIntAddrRange(AddrRangeList &range_list); 2335651Sgblack@eecs.umich.edu 2345654Sgblack@eecs.umich.edu Port *getPort(const std::string &if_name, int idx = -1) 2355654Sgblack@eecs.umich.edu { 2365654Sgblack@eecs.umich.edu if (if_name == "int_port") 2375654Sgblack@eecs.umich.edu return intPort; 2385654Sgblack@eecs.umich.edu return BasicPioDevice::getPort(if_name, idx); 2395654Sgblack@eecs.umich.edu } 2405654Sgblack@eecs.umich.edu 2415654Sgblack@eecs.umich.edu /* 2425654Sgblack@eecs.umich.edu * Functions to access and manipulate the APIC's registers. 2435654Sgblack@eecs.umich.edu */ 2445654Sgblack@eecs.umich.edu 2455648Sgblack@eecs.umich.edu uint32_t readReg(ApicRegIndex miscReg); 2465648Sgblack@eecs.umich.edu void setReg(ApicRegIndex reg, uint32_t val); 2475704Snate@binkert.org void 2485704Snate@binkert.org setRegNoEffect(ApicRegIndex reg, uint32_t val) 2495647Sgblack@eecs.umich.edu { 2505648Sgblack@eecs.umich.edu regs[reg] = val; 2515648Sgblack@eecs.umich.edu } 2525648Sgblack@eecs.umich.edu 2535654Sgblack@eecs.umich.edu /* 2545654Sgblack@eecs.umich.edu * Constructor. 2555654Sgblack@eecs.umich.edu */ 2565654Sgblack@eecs.umich.edu 2576041Sgblack@eecs.umich.edu Interrupts(Params * p); 2585086Sgblack@eecs.umich.edu 2595654Sgblack@eecs.umich.edu /* 2605654Sgblack@eecs.umich.edu * Functions for retrieving interrupts for the CPU to handle. 2615654Sgblack@eecs.umich.edu */ 2625651Sgblack@eecs.umich.edu 2635704Snate@binkert.org bool checkInterrupts(ThreadContext *tc) const; 2645704Snate@binkert.org Fault getInterrupt(ThreadContext *tc); 2655704Snate@binkert.org void updateIntrInfo(ThreadContext *tc); 2665086Sgblack@eecs.umich.edu 2675654Sgblack@eecs.umich.edu /* 2685654Sgblack@eecs.umich.edu * Serialization. 2695654Sgblack@eecs.umich.edu */ 2705086Sgblack@eecs.umich.edu 2715704Snate@binkert.org void 2725704Snate@binkert.org serialize(std::ostream &os) 2735086Sgblack@eecs.umich.edu { 2745133Sgblack@eecs.umich.edu panic("Interrupts::serialize unimplemented!\n"); 2755086Sgblack@eecs.umich.edu } 2765086Sgblack@eecs.umich.edu 2775704Snate@binkert.org void 2785704Snate@binkert.org unserialize(Checkpoint *cp, const std::string §ion) 2795086Sgblack@eecs.umich.edu { 2805133Sgblack@eecs.umich.edu panic("Interrupts::unserialize unimplemented!\n"); 2815086Sgblack@eecs.umich.edu } 2825654Sgblack@eecs.umich.edu 2835654Sgblack@eecs.umich.edu /* 2845654Sgblack@eecs.umich.edu * Old functions needed for compatability but which will be phased out 2855654Sgblack@eecs.umich.edu * eventually. 2865654Sgblack@eecs.umich.edu */ 2875704Snate@binkert.org void 2885704Snate@binkert.org post(int int_num, int index) 2895654Sgblack@eecs.umich.edu { 2905654Sgblack@eecs.umich.edu panic("Interrupts::post unimplemented!\n"); 2915654Sgblack@eecs.umich.edu } 2925654Sgblack@eecs.umich.edu 2935704Snate@binkert.org void 2945704Snate@binkert.org clear(int int_num, int index) 2955654Sgblack@eecs.umich.edu { 2965654Sgblack@eecs.umich.edu panic("Interrupts::clear unimplemented!\n"); 2975654Sgblack@eecs.umich.edu } 2985654Sgblack@eecs.umich.edu 2995704Snate@binkert.org void 3005704Snate@binkert.org clearAll() 3015654Sgblack@eecs.umich.edu { 3025704Snate@binkert.org panic("Interrupts::clearAll unimplemented!\n"); 3035654Sgblack@eecs.umich.edu } 3045086Sgblack@eecs.umich.edu}; 3055086Sgblack@eecs.umich.edu 3065704Snate@binkert.org} // namespace X86ISA 3074120Sgblack@eecs.umich.edu 3084120Sgblack@eecs.umich.edu#endif // __ARCH_X86_INTERRUPTS_HH__ 309