interrupts.hh revision 5655
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IN NO EVENT SHALL THE COPYRIGHT 474120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544120Sgblack@eecs.umich.edu * 554120Sgblack@eecs.umich.edu * Authors: Gabe Black 564120Sgblack@eecs.umich.edu */ 574120Sgblack@eecs.umich.edu 584120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_INTERRUPTS_HH__ 594120Sgblack@eecs.umich.edu#define __ARCH_X86_INTERRUPTS_HH__ 604120Sgblack@eecs.umich.edu 615647Sgblack@eecs.umich.edu#include "arch/x86/apicregs.hh" 625086Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 635655Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 645654Sgblack@eecs.umich.edu#include "base/bitfield.hh" 655086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 665648Sgblack@eecs.umich.edu#include "dev/io_device.hh" 675651Sgblack@eecs.umich.edu#include "dev/x86/intdev.hh" 685647Sgblack@eecs.umich.edu#include "params/X86LocalApic.hh" 695647Sgblack@eecs.umich.edu#include "sim/eventq.hh" 705647Sgblack@eecs.umich.edu 715647Sgblack@eecs.umich.educlass ThreadContext; 724120Sgblack@eecs.umich.edu 734120Sgblack@eecs.umich.edunamespace X86ISA 744120Sgblack@eecs.umich.edu{ 755086Sgblack@eecs.umich.edu 765651Sgblack@eecs.umich.educlass Interrupts : public BasicPioDevice, IntDev 775086Sgblack@eecs.umich.edu{ 785647Sgblack@eecs.umich.edu protected: 795654Sgblack@eecs.umich.edu // Storage for the APIC registers 805647Sgblack@eecs.umich.edu uint32_t regs[NUM_APIC_REGS]; 815654Sgblack@eecs.umich.edu 825654Sgblack@eecs.umich.edu /* 835654Sgblack@eecs.umich.edu * Timing related stuff. 845654Sgblack@eecs.umich.edu */ 855648Sgblack@eecs.umich.edu Tick latency; 865648Sgblack@eecs.umich.edu Tick clock; 875647Sgblack@eecs.umich.edu 885647Sgblack@eecs.umich.edu class ApicTimerEvent : public Event 895647Sgblack@eecs.umich.edu { 905647Sgblack@eecs.umich.edu public: 915647Sgblack@eecs.umich.edu ApicTimerEvent() : Event() 925647Sgblack@eecs.umich.edu {} 935647Sgblack@eecs.umich.edu 945647Sgblack@eecs.umich.edu void process() 955647Sgblack@eecs.umich.edu { 965647Sgblack@eecs.umich.edu warn("Local APIC timer event doesn't do anything!\n"); 975647Sgblack@eecs.umich.edu } 985647Sgblack@eecs.umich.edu }; 995647Sgblack@eecs.umich.edu 1005647Sgblack@eecs.umich.edu ApicTimerEvent apicTimerEvent; 1015647Sgblack@eecs.umich.edu 1025654Sgblack@eecs.umich.edu /* 1035655Sgblack@eecs.umich.edu * A set of variables to keep track of interrupts that don't go through 1045655Sgblack@eecs.umich.edu * the IRR. 1055655Sgblack@eecs.umich.edu */ 1065655Sgblack@eecs.umich.edu bool pendingSmi; 1075655Sgblack@eecs.umich.edu TriggerIntMessage smiMessage; 1085655Sgblack@eecs.umich.edu bool pendingNmi; 1095655Sgblack@eecs.umich.edu TriggerIntMessage nmiMessage; 1105655Sgblack@eecs.umich.edu bool pendingExtInt; 1115655Sgblack@eecs.umich.edu TriggerIntMessage extIntMessage; 1125655Sgblack@eecs.umich.edu bool pendingInit; 1135655Sgblack@eecs.umich.edu TriggerIntMessage initMessage; 1145655Sgblack@eecs.umich.edu 1155655Sgblack@eecs.umich.edu // This is a quick check whether any of the above (except ExtInt) are set. 1165655Sgblack@eecs.umich.edu bool pendingUnmaskableInt; 1175655Sgblack@eecs.umich.edu 1185655Sgblack@eecs.umich.edu /* 1195654Sgblack@eecs.umich.edu * IRR and ISR maintenance. 1205654Sgblack@eecs.umich.edu */ 1215654Sgblack@eecs.umich.edu uint8_t IRRV; 1225654Sgblack@eecs.umich.edu uint8_t ISRV; 1235654Sgblack@eecs.umich.edu 1245654Sgblack@eecs.umich.edu int 1255654Sgblack@eecs.umich.edu findRegArrayMSB(ApicRegIndex base) 1265654Sgblack@eecs.umich.edu { 1275654Sgblack@eecs.umich.edu int offset = 7; 1285654Sgblack@eecs.umich.edu do { 1295654Sgblack@eecs.umich.edu if (regs[base + offset] != 0) { 1305654Sgblack@eecs.umich.edu return offset * 32 + findMsbSet(regs[base + offset]); 1315654Sgblack@eecs.umich.edu } 1325654Sgblack@eecs.umich.edu } while (offset--); 1335654Sgblack@eecs.umich.edu return 0; 1345654Sgblack@eecs.umich.edu } 1355654Sgblack@eecs.umich.edu 1365654Sgblack@eecs.umich.edu void 1375654Sgblack@eecs.umich.edu updateIRRV() 1385654Sgblack@eecs.umich.edu { 1395654Sgblack@eecs.umich.edu IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE); 1405654Sgblack@eecs.umich.edu } 1415654Sgblack@eecs.umich.edu 1425654Sgblack@eecs.umich.edu void 1435654Sgblack@eecs.umich.edu updateISRV() 1445654Sgblack@eecs.umich.edu { 1455654Sgblack@eecs.umich.edu ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE); 1465654Sgblack@eecs.umich.edu } 1475654Sgblack@eecs.umich.edu 1485654Sgblack@eecs.umich.edu void 1495654Sgblack@eecs.umich.edu setRegArrayBit(ApicRegIndex base, uint8_t vector) 1505654Sgblack@eecs.umich.edu { 1515654Sgblack@eecs.umich.edu regs[base + (vector % 32)] |= (1 << (vector >> 5)); 1525654Sgblack@eecs.umich.edu } 1535654Sgblack@eecs.umich.edu 1545654Sgblack@eecs.umich.edu void 1555654Sgblack@eecs.umich.edu clearRegArrayBit(ApicRegIndex base, uint8_t vector) 1565654Sgblack@eecs.umich.edu { 1575654Sgblack@eecs.umich.edu regs[base + (vector % 32)] &= ~(1 << (vector >> 5)); 1585654Sgblack@eecs.umich.edu } 1595654Sgblack@eecs.umich.edu 1605654Sgblack@eecs.umich.edu bool 1615654Sgblack@eecs.umich.edu getRegArrayBit(ApicRegIndex base, uint8_t vector) 1625654Sgblack@eecs.umich.edu { 1635654Sgblack@eecs.umich.edu return bits(regs[base + (vector % 32)], vector >> 5); 1645654Sgblack@eecs.umich.edu } 1655654Sgblack@eecs.umich.edu 1665086Sgblack@eecs.umich.edu public: 1675654Sgblack@eecs.umich.edu /* 1685654Sgblack@eecs.umich.edu * Params stuff. 1695654Sgblack@eecs.umich.edu */ 1705647Sgblack@eecs.umich.edu typedef X86LocalApicParams Params; 1715647Sgblack@eecs.umich.edu 1725648Sgblack@eecs.umich.edu void setClock(Tick newClock) 1735648Sgblack@eecs.umich.edu { 1745648Sgblack@eecs.umich.edu clock = newClock; 1755648Sgblack@eecs.umich.edu } 1765648Sgblack@eecs.umich.edu 1775647Sgblack@eecs.umich.edu const Params * 1785647Sgblack@eecs.umich.edu params() const 1795086Sgblack@eecs.umich.edu { 1805647Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 1815647Sgblack@eecs.umich.edu } 1825647Sgblack@eecs.umich.edu 1835654Sgblack@eecs.umich.edu /* 1845654Sgblack@eecs.umich.edu * Functions to interact with the interrupt port from IntDev. 1855654Sgblack@eecs.umich.edu */ 1865648Sgblack@eecs.umich.edu Tick read(PacketPtr pkt); 1875648Sgblack@eecs.umich.edu Tick write(PacketPtr pkt); 1885651Sgblack@eecs.umich.edu Tick recvMessage(PacketPtr pkt); 1895647Sgblack@eecs.umich.edu 1905648Sgblack@eecs.umich.edu void addressRanges(AddrRangeList &range_list) 1915648Sgblack@eecs.umich.edu { 1925648Sgblack@eecs.umich.edu range_list.clear(); 1935648Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86LocalAPICAddress(0, 0), 1945648Sgblack@eecs.umich.edu x86LocalAPICAddress(0, 0) + PageBytes)); 1955648Sgblack@eecs.umich.edu } 1965647Sgblack@eecs.umich.edu 1975651Sgblack@eecs.umich.edu void getIntAddrRange(AddrRangeList &range_list) 1985651Sgblack@eecs.umich.edu { 1995651Sgblack@eecs.umich.edu range_list.clear(); 2005651Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86InterruptAddress(0, 0), 2015651Sgblack@eecs.umich.edu x86InterruptAddress(0, 0) + PhysAddrAPICRangeSize)); 2025651Sgblack@eecs.umich.edu } 2035651Sgblack@eecs.umich.edu 2045654Sgblack@eecs.umich.edu Port *getPort(const std::string &if_name, int idx = -1) 2055654Sgblack@eecs.umich.edu { 2065654Sgblack@eecs.umich.edu if (if_name == "int_port") 2075654Sgblack@eecs.umich.edu return intPort; 2085654Sgblack@eecs.umich.edu return BasicPioDevice::getPort(if_name, idx); 2095654Sgblack@eecs.umich.edu } 2105654Sgblack@eecs.umich.edu 2115654Sgblack@eecs.umich.edu /* 2125654Sgblack@eecs.umich.edu * Functions to access and manipulate the APIC's registers. 2135654Sgblack@eecs.umich.edu */ 2145654Sgblack@eecs.umich.edu 2155648Sgblack@eecs.umich.edu uint32_t readReg(ApicRegIndex miscReg); 2165648Sgblack@eecs.umich.edu void setReg(ApicRegIndex reg, uint32_t val); 2175648Sgblack@eecs.umich.edu void setRegNoEffect(ApicRegIndex reg, uint32_t val) 2185647Sgblack@eecs.umich.edu { 2195648Sgblack@eecs.umich.edu regs[reg] = val; 2205648Sgblack@eecs.umich.edu } 2215648Sgblack@eecs.umich.edu 2225654Sgblack@eecs.umich.edu /* 2235654Sgblack@eecs.umich.edu * Constructor. 2245654Sgblack@eecs.umich.edu */ 2255654Sgblack@eecs.umich.edu 2265651Sgblack@eecs.umich.edu Interrupts(Params * p) : BasicPioDevice(p), IntDev(this), 2275655Sgblack@eecs.umich.edu latency(p->pio_latency), clock(0), 2285655Sgblack@eecs.umich.edu pendingSmi(false), smiMessage(0), 2295655Sgblack@eecs.umich.edu pendingNmi(false), nmiMessage(0), 2305655Sgblack@eecs.umich.edu pendingExtInt(false), extIntMessage(0), 2315655Sgblack@eecs.umich.edu pendingInit(false), initMessage(0), 2325655Sgblack@eecs.umich.edu pendingUnmaskableInt(false) 2335648Sgblack@eecs.umich.edu { 2345648Sgblack@eecs.umich.edu pioSize = PageBytes; 2355654Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 2365647Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 2375647Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 2385654Sgblack@eecs.umich.edu ISRV = 0; 2395654Sgblack@eecs.umich.edu IRRV = 0; 2405086Sgblack@eecs.umich.edu } 2415086Sgblack@eecs.umich.edu 2425654Sgblack@eecs.umich.edu /* 2435654Sgblack@eecs.umich.edu * Functions for retrieving interrupts for the CPU to handle. 2445654Sgblack@eecs.umich.edu */ 2455651Sgblack@eecs.umich.edu 2465654Sgblack@eecs.umich.edu bool check_interrupts(ThreadContext * tc) const; 2475654Sgblack@eecs.umich.edu Fault getInterrupt(ThreadContext * tc); 2485654Sgblack@eecs.umich.edu void updateIntrInfo(ThreadContext * tc); 2495086Sgblack@eecs.umich.edu 2505654Sgblack@eecs.umich.edu /* 2515654Sgblack@eecs.umich.edu * Serialization. 2525654Sgblack@eecs.umich.edu */ 2535086Sgblack@eecs.umich.edu 2545086Sgblack@eecs.umich.edu void serialize(std::ostream & os) 2555086Sgblack@eecs.umich.edu { 2565133Sgblack@eecs.umich.edu panic("Interrupts::serialize unimplemented!\n"); 2575086Sgblack@eecs.umich.edu } 2585086Sgblack@eecs.umich.edu 2595086Sgblack@eecs.umich.edu void unserialize(Checkpoint * cp, const std::string & section) 2605086Sgblack@eecs.umich.edu { 2615133Sgblack@eecs.umich.edu panic("Interrupts::unserialize unimplemented!\n"); 2625086Sgblack@eecs.umich.edu } 2635654Sgblack@eecs.umich.edu 2645654Sgblack@eecs.umich.edu /* 2655654Sgblack@eecs.umich.edu * Old functions needed for compatability but which will be phased out 2665654Sgblack@eecs.umich.edu * eventually. 2675654Sgblack@eecs.umich.edu */ 2685654Sgblack@eecs.umich.edu void post(int int_num, int index) 2695654Sgblack@eecs.umich.edu { 2705654Sgblack@eecs.umich.edu panic("Interrupts::post unimplemented!\n"); 2715654Sgblack@eecs.umich.edu } 2725654Sgblack@eecs.umich.edu 2735654Sgblack@eecs.umich.edu void clear(int int_num, int index) 2745654Sgblack@eecs.umich.edu { 2755654Sgblack@eecs.umich.edu panic("Interrupts::clear unimplemented!\n"); 2765654Sgblack@eecs.umich.edu } 2775654Sgblack@eecs.umich.edu 2785654Sgblack@eecs.umich.edu void clear_all() 2795654Sgblack@eecs.umich.edu { 2805654Sgblack@eecs.umich.edu panic("Interrupts::clear_all unimplemented!\n"); 2815654Sgblack@eecs.umich.edu } 2825086Sgblack@eecs.umich.edu}; 2835086Sgblack@eecs.umich.edu 2844120Sgblack@eecs.umich.edu}; 2854120Sgblack@eecs.umich.edu 2864120Sgblack@eecs.umich.edu#endif // __ARCH_X86_INTERRUPTS_HH__ 287