interrupts.hh revision 12124
14120Sgblack@eecs.umich.edu/* 28839Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38839Sandreas.hansson@arm.com * All rights reserved 48839Sandreas.hansson@arm.com * 58839Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68839Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78839Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88839Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98839Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108839Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118839Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128839Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138839Sandreas.hansson@arm.com * 144120Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 154120Sgblack@eecs.umich.edu * All rights reserved. 164120Sgblack@eecs.umich.edu * 177087Snate@binkert.org * The license below extends only to copyright in the software and shall 187087Snate@binkert.org * not be construed as granting a license to any other intellectual 197087Snate@binkert.org * property including but not limited to intellectual property relating 207087Snate@binkert.org * to a hardware implementation of the functionality of the software 217087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 227087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 237087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 247087Snate@binkert.org * modified or unmodified, in source code or in binary form. 254120Sgblack@eecs.umich.edu * 267087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 277087Snate@binkert.org * modification, are permitted provided that the following conditions are 287087Snate@binkert.org * met: redistributions of source code must retain the above copyright 297087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 307087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 317087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 327087Snate@binkert.org * documentation and/or other materials provided with the distribution; 337087Snate@binkert.org * neither the name of the copyright holders nor the names of its 344120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 357087Snate@binkert.org * this software without specific prior written permission. 364120Sgblack@eecs.umich.edu * 374120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 384120Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 394120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 404120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 414120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 424120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 434120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 444120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 454120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 464120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 474120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 484120Sgblack@eecs.umich.edu * 494120Sgblack@eecs.umich.edu * Authors: Gabe Black 508839Sandreas.hansson@arm.com * Andreas Hansson 514120Sgblack@eecs.umich.edu */ 524120Sgblack@eecs.umich.edu 534120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_INTERRUPTS_HH__ 544120Sgblack@eecs.umich.edu#define __ARCH_X86_INTERRUPTS_HH__ 554120Sgblack@eecs.umich.edu 568229Snate@binkert.org#include "arch/x86/regs/apic.hh" 575086Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 585655Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 595654Sgblack@eecs.umich.edu#include "base/bitfield.hh" 605086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 618229Snate@binkert.org#include "dev/x86/intdev.hh" 625648Sgblack@eecs.umich.edu#include "dev/io_device.hh" 635647Sgblack@eecs.umich.edu#include "params/X86LocalApic.hh" 645647Sgblack@eecs.umich.edu#include "sim/eventq.hh" 655647Sgblack@eecs.umich.edu 665647Sgblack@eecs.umich.educlass ThreadContext; 675810Sgblack@eecs.umich.educlass BaseCPU; 684120Sgblack@eecs.umich.edu 699554Sandreas.hansson@arm.comint divideFromConf(uint32_t conf); 709554Sandreas.hansson@arm.com 715704Snate@binkert.orgnamespace X86ISA { 725086Sgblack@eecs.umich.edu 739554Sandreas.hansson@arm.comApicRegIndex decodeAddr(Addr paddr); 749554Sandreas.hansson@arm.com 759807Sstever@gmail.comclass Interrupts : public BasicPioDevice, IntDevice 765086Sgblack@eecs.umich.edu{ 775647Sgblack@eecs.umich.edu protected: 785654Sgblack@eecs.umich.edu // Storage for the APIC registers 795647Sgblack@eecs.umich.edu uint32_t regs[NUM_APIC_REGS]; 805654Sgblack@eecs.umich.edu 815691Sgblack@eecs.umich.edu BitUnion32(LVTEntry) 825691Sgblack@eecs.umich.edu Bitfield<7, 0> vector; 835691Sgblack@eecs.umich.edu Bitfield<10, 8> deliveryMode; 845691Sgblack@eecs.umich.edu Bitfield<12> status; 855691Sgblack@eecs.umich.edu Bitfield<13> polarity; 865691Sgblack@eecs.umich.edu Bitfield<14> remoteIRR; 875691Sgblack@eecs.umich.edu Bitfield<15> trigger; 885691Sgblack@eecs.umich.edu Bitfield<16> masked; 895691Sgblack@eecs.umich.edu Bitfield<17> periodic; 905691Sgblack@eecs.umich.edu EndBitUnion(LVTEntry) 915691Sgblack@eecs.umich.edu 925654Sgblack@eecs.umich.edu /* 935654Sgblack@eecs.umich.edu * Timing related stuff. 945654Sgblack@eecs.umich.edu */ 9512124Sspwilson2@wisc.edu EventFunctionWrapper apicTimerEvent; 9612124Sspwilson2@wisc.edu void processApicTimerEvent(); 975647Sgblack@eecs.umich.edu 985654Sgblack@eecs.umich.edu /* 995655Sgblack@eecs.umich.edu * A set of variables to keep track of interrupts that don't go through 1005655Sgblack@eecs.umich.edu * the IRR. 1015655Sgblack@eecs.umich.edu */ 1025655Sgblack@eecs.umich.edu bool pendingSmi; 1035691Sgblack@eecs.umich.edu uint8_t smiVector; 1045655Sgblack@eecs.umich.edu bool pendingNmi; 1055691Sgblack@eecs.umich.edu uint8_t nmiVector; 1065655Sgblack@eecs.umich.edu bool pendingExtInt; 1075691Sgblack@eecs.umich.edu uint8_t extIntVector; 1085655Sgblack@eecs.umich.edu bool pendingInit; 1095691Sgblack@eecs.umich.edu uint8_t initVector; 1106050Sgblack@eecs.umich.edu bool pendingStartup; 1116050Sgblack@eecs.umich.edu uint8_t startupVector; 1126066Sgblack@eecs.umich.edu bool startedUp; 1135655Sgblack@eecs.umich.edu 1145655Sgblack@eecs.umich.edu // This is a quick check whether any of the above (except ExtInt) are set. 1155655Sgblack@eecs.umich.edu bool pendingUnmaskableInt; 1165655Sgblack@eecs.umich.edu 1176069Sgblack@eecs.umich.edu // A count of how many IPIs are in flight. 1186069Sgblack@eecs.umich.edu int pendingIPIs; 1196069Sgblack@eecs.umich.edu 1205655Sgblack@eecs.umich.edu /* 1215654Sgblack@eecs.umich.edu * IRR and ISR maintenance. 1225654Sgblack@eecs.umich.edu */ 1235654Sgblack@eecs.umich.edu uint8_t IRRV; 1245654Sgblack@eecs.umich.edu uint8_t ISRV; 1255654Sgblack@eecs.umich.edu 1265654Sgblack@eecs.umich.edu int 1275654Sgblack@eecs.umich.edu findRegArrayMSB(ApicRegIndex base) 1285654Sgblack@eecs.umich.edu { 1295654Sgblack@eecs.umich.edu int offset = 7; 1305654Sgblack@eecs.umich.edu do { 1315654Sgblack@eecs.umich.edu if (regs[base + offset] != 0) { 1325654Sgblack@eecs.umich.edu return offset * 32 + findMsbSet(regs[base + offset]); 1335654Sgblack@eecs.umich.edu } 1345654Sgblack@eecs.umich.edu } while (offset--); 1355654Sgblack@eecs.umich.edu return 0; 1365654Sgblack@eecs.umich.edu } 1375654Sgblack@eecs.umich.edu 1385654Sgblack@eecs.umich.edu void 1395654Sgblack@eecs.umich.edu updateIRRV() 1405654Sgblack@eecs.umich.edu { 1415654Sgblack@eecs.umich.edu IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE); 1425654Sgblack@eecs.umich.edu } 1435654Sgblack@eecs.umich.edu 1445654Sgblack@eecs.umich.edu void 1455654Sgblack@eecs.umich.edu updateISRV() 1465654Sgblack@eecs.umich.edu { 1475654Sgblack@eecs.umich.edu ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE); 1485654Sgblack@eecs.umich.edu } 1495654Sgblack@eecs.umich.edu 1505654Sgblack@eecs.umich.edu void 1515654Sgblack@eecs.umich.edu setRegArrayBit(ApicRegIndex base, uint8_t vector) 1525654Sgblack@eecs.umich.edu { 1536101Sgblack@eecs.umich.edu regs[base + (vector / 32)] |= (1 << (vector % 32)); 1545654Sgblack@eecs.umich.edu } 1555654Sgblack@eecs.umich.edu 1565654Sgblack@eecs.umich.edu void 1575654Sgblack@eecs.umich.edu clearRegArrayBit(ApicRegIndex base, uint8_t vector) 1585654Sgblack@eecs.umich.edu { 1596101Sgblack@eecs.umich.edu regs[base + (vector / 32)] &= ~(1 << (vector % 32)); 1605654Sgblack@eecs.umich.edu } 1615654Sgblack@eecs.umich.edu 1625654Sgblack@eecs.umich.edu bool 1635654Sgblack@eecs.umich.edu getRegArrayBit(ApicRegIndex base, uint8_t vector) 1645654Sgblack@eecs.umich.edu { 16510541Sgabeblack@google.com return bits(regs[base + (vector / 32)], vector % 32); 1665654Sgblack@eecs.umich.edu } 1675654Sgblack@eecs.umich.edu 1685691Sgblack@eecs.umich.edu void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level); 1695691Sgblack@eecs.umich.edu 1705810Sgblack@eecs.umich.edu BaseCPU *cpu; 1715810Sgblack@eecs.umich.edu 1726136Sgblack@eecs.umich.edu int initialApicId; 1736136Sgblack@eecs.umich.edu 1748851Sandreas.hansson@arm.com // Port for receiving interrupts 1758922Swilliam.wang@arm.com IntSlavePort intSlavePort; 1768851Sandreas.hansson@arm.com 1775086Sgblack@eecs.umich.edu public: 1788742Sgblack@eecs.umich.edu 1798746Sgblack@eecs.umich.edu int getInitialApicId() { return initialApicId; } 1808746Sgblack@eecs.umich.edu 1815654Sgblack@eecs.umich.edu /* 1825654Sgblack@eecs.umich.edu * Params stuff. 1835654Sgblack@eecs.umich.edu */ 1845647Sgblack@eecs.umich.edu typedef X86LocalApicParams Params; 1855647Sgblack@eecs.umich.edu 1866041Sgblack@eecs.umich.edu void setCPU(BaseCPU * newCPU); 1875810Sgblack@eecs.umich.edu 1885647Sgblack@eecs.umich.edu const Params * 1895647Sgblack@eecs.umich.edu params() const 1905086Sgblack@eecs.umich.edu { 1915647Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 1925647Sgblack@eecs.umich.edu } 1935647Sgblack@eecs.umich.edu 1945654Sgblack@eecs.umich.edu /* 1956137Sgblack@eecs.umich.edu * Initialize this object by registering it with the IO APIC. 1966137Sgblack@eecs.umich.edu */ 19711175Sandreas.hansson@arm.com void init() override; 1986137Sgblack@eecs.umich.edu 1996137Sgblack@eecs.umich.edu /* 2009807Sstever@gmail.com * Functions to interact with the interrupt port from IntDevice. 2015654Sgblack@eecs.umich.edu */ 20211175Sandreas.hansson@arm.com Tick read(PacketPtr pkt) override; 20311175Sandreas.hansson@arm.com Tick write(PacketPtr pkt) override; 20411175Sandreas.hansson@arm.com Tick recvMessage(PacketPtr pkt) override; 20511175Sandreas.hansson@arm.com Tick recvResponse(PacketPtr pkt) override; 2065647Sgblack@eecs.umich.edu 2075691Sgblack@eecs.umich.edu bool 2085691Sgblack@eecs.umich.edu triggerTimerInterrupt() 2095691Sgblack@eecs.umich.edu { 2105691Sgblack@eecs.umich.edu LVTEntry entry = regs[APIC_LVT_TIMER]; 2115691Sgblack@eecs.umich.edu if (!entry.masked) 2125691Sgblack@eecs.umich.edu requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger); 2135691Sgblack@eecs.umich.edu return entry.periodic; 2145691Sgblack@eecs.umich.edu } 2155691Sgblack@eecs.umich.edu 21611175Sandreas.hansson@arm.com AddrRangeList getIntAddrRange() const override; 2175651Sgblack@eecs.umich.edu 2189294Sandreas.hansson@arm.com BaseMasterPort &getMasterPort(const std::string &if_name, 21911175Sandreas.hansson@arm.com PortID idx = InvalidPortID) override 2205654Sgblack@eecs.umich.edu { 2218839Sandreas.hansson@arm.com if (if_name == "int_master") { 2228922Swilliam.wang@arm.com return intMasterPort; 2238839Sandreas.hansson@arm.com } 2248922Swilliam.wang@arm.com return BasicPioDevice::getMasterPort(if_name, idx); 2258922Swilliam.wang@arm.com } 2268922Swilliam.wang@arm.com 2279294Sandreas.hansson@arm.com BaseSlavePort &getSlavePort(const std::string &if_name, 22811175Sandreas.hansson@arm.com PortID idx = InvalidPortID) override 2298922Swilliam.wang@arm.com { 2308922Swilliam.wang@arm.com if (if_name == "int_slave") { 2318922Swilliam.wang@arm.com return intSlavePort; 2328922Swilliam.wang@arm.com } 2338922Swilliam.wang@arm.com return BasicPioDevice::getSlavePort(if_name, idx); 2345654Sgblack@eecs.umich.edu } 2355654Sgblack@eecs.umich.edu 2365654Sgblack@eecs.umich.edu /* 2375654Sgblack@eecs.umich.edu * Functions to access and manipulate the APIC's registers. 2385654Sgblack@eecs.umich.edu */ 2395654Sgblack@eecs.umich.edu 2405648Sgblack@eecs.umich.edu uint32_t readReg(ApicRegIndex miscReg); 2415648Sgblack@eecs.umich.edu void setReg(ApicRegIndex reg, uint32_t val); 2425704Snate@binkert.org void 2435704Snate@binkert.org setRegNoEffect(ApicRegIndex reg, uint32_t val) 2445647Sgblack@eecs.umich.edu { 2455648Sgblack@eecs.umich.edu regs[reg] = val; 2465648Sgblack@eecs.umich.edu } 2475648Sgblack@eecs.umich.edu 2485654Sgblack@eecs.umich.edu /* 2495654Sgblack@eecs.umich.edu * Constructor. 2505654Sgblack@eecs.umich.edu */ 2515654Sgblack@eecs.umich.edu 2526041Sgblack@eecs.umich.edu Interrupts(Params * p); 2535086Sgblack@eecs.umich.edu 2545654Sgblack@eecs.umich.edu /* 2555654Sgblack@eecs.umich.edu * Functions for retrieving interrupts for the CPU to handle. 2565654Sgblack@eecs.umich.edu */ 2575651Sgblack@eecs.umich.edu 2585704Snate@binkert.org bool checkInterrupts(ThreadContext *tc) const; 2599874Sandreas@sandberg.pp.se /** 2609874Sandreas@sandberg.pp.se * Check if there are pending interrupts without ignoring the 2619874Sandreas@sandberg.pp.se * interrupts disabled flag. 2629874Sandreas@sandberg.pp.se * 2639874Sandreas@sandberg.pp.se * @return true if there are interrupts pending. 2649874Sandreas@sandberg.pp.se */ 2659874Sandreas@sandberg.pp.se bool checkInterruptsRaw() const; 26610112Sandreas@sandberg.pp.se /** 26710112Sandreas@sandberg.pp.se * Check if there are pending unmaskable interrupts. 26810112Sandreas@sandberg.pp.se * 26910112Sandreas@sandberg.pp.se * @return true there are unmaskable interrupts pending. 27010112Sandreas@sandberg.pp.se */ 27110112Sandreas@sandberg.pp.se bool hasPendingUnmaskable() const { return pendingUnmaskableInt; } 2725704Snate@binkert.org Fault getInterrupt(ThreadContext *tc); 2735704Snate@binkert.org void updateIntrInfo(ThreadContext *tc); 2745086Sgblack@eecs.umich.edu 2755654Sgblack@eecs.umich.edu /* 2765654Sgblack@eecs.umich.edu * Serialization. 2775654Sgblack@eecs.umich.edu */ 27811168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 27911168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 2805654Sgblack@eecs.umich.edu 2815654Sgblack@eecs.umich.edu /* 2825654Sgblack@eecs.umich.edu * Old functions needed for compatability but which will be phased out 2835654Sgblack@eecs.umich.edu * eventually. 2845654Sgblack@eecs.umich.edu */ 2855704Snate@binkert.org void 2865704Snate@binkert.org post(int int_num, int index) 2875654Sgblack@eecs.umich.edu { 2885654Sgblack@eecs.umich.edu panic("Interrupts::post unimplemented!\n"); 2895654Sgblack@eecs.umich.edu } 2905654Sgblack@eecs.umich.edu 2915704Snate@binkert.org void 2925704Snate@binkert.org clear(int int_num, int index) 2935654Sgblack@eecs.umich.edu { 2945654Sgblack@eecs.umich.edu panic("Interrupts::clear unimplemented!\n"); 2955654Sgblack@eecs.umich.edu } 2965654Sgblack@eecs.umich.edu 2975704Snate@binkert.org void 2985704Snate@binkert.org clearAll() 2995654Sgblack@eecs.umich.edu { 3005704Snate@binkert.org panic("Interrupts::clearAll unimplemented!\n"); 3015654Sgblack@eecs.umich.edu } 3025086Sgblack@eecs.umich.edu}; 3035086Sgblack@eecs.umich.edu 3045704Snate@binkert.org} // namespace X86ISA 3054120Sgblack@eecs.umich.edu 3064120Sgblack@eecs.umich.edu#endif // __ARCH_X86_INTERRUPTS_HH__ 307