interrupts.cc revision 8768:314eb1e2fa94 
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/x86/regs/apic.hh"
41#include "arch/x86/interrupts.hh"
42#include "arch/x86/intmessage.hh"
43#include "config/full_system.hh"
44#include "cpu/base.hh"
45#include "debug/LocalApic.hh"
46#include "dev/x86/i82094aa.hh"
47#include "dev/x86/pc.hh"
48#include "dev/x86/south_bridge.hh"
49#include "mem/packet_access.hh"
50#include "sim/system.hh"
51
52int
53divideFromConf(uint32_t conf)
54{
55    // This figures out what division we want from the division configuration
56    // register in the local APIC. The encoding is a little odd but it can
57    // be deciphered fairly easily.
58    int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
59    shift = (shift + 1) % 8;
60    return 1 << shift;
61}
62
63namespace X86ISA
64{
65
66ApicRegIndex
67decodeAddr(Addr paddr)
68{
69    ApicRegIndex regNum;
70    paddr &= ~mask(3);
71    switch (paddr)
72    {
73      case 0x20:
74        regNum = APIC_ID;
75        break;
76      case 0x30:
77        regNum = APIC_VERSION;
78        break;
79      case 0x80:
80        regNum = APIC_TASK_PRIORITY;
81        break;
82      case 0x90:
83        regNum = APIC_ARBITRATION_PRIORITY;
84        break;
85      case 0xA0:
86        regNum = APIC_PROCESSOR_PRIORITY;
87        break;
88      case 0xB0:
89        regNum = APIC_EOI;
90        break;
91      case 0xD0:
92        regNum = APIC_LOGICAL_DESTINATION;
93        break;
94      case 0xE0:
95        regNum = APIC_DESTINATION_FORMAT;
96        break;
97      case 0xF0:
98        regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
99        break;
100      case 0x100:
101      case 0x108:
102      case 0x110:
103      case 0x118:
104      case 0x120:
105      case 0x128:
106      case 0x130:
107      case 0x138:
108      case 0x140:
109      case 0x148:
110      case 0x150:
111      case 0x158:
112      case 0x160:
113      case 0x168:
114      case 0x170:
115      case 0x178:
116        regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
117        break;
118      case 0x180:
119      case 0x188:
120      case 0x190:
121      case 0x198:
122      case 0x1A0:
123      case 0x1A8:
124      case 0x1B0:
125      case 0x1B8:
126      case 0x1C0:
127      case 0x1C8:
128      case 0x1D0:
129      case 0x1D8:
130      case 0x1E0:
131      case 0x1E8:
132      case 0x1F0:
133      case 0x1F8:
134        regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
135        break;
136      case 0x200:
137      case 0x208:
138      case 0x210:
139      case 0x218:
140      case 0x220:
141      case 0x228:
142      case 0x230:
143      case 0x238:
144      case 0x240:
145      case 0x248:
146      case 0x250:
147      case 0x258:
148      case 0x260:
149      case 0x268:
150      case 0x270:
151      case 0x278:
152        regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
153        break;
154      case 0x280:
155        regNum = APIC_ERROR_STATUS;
156        break;
157      case 0x300:
158        regNum = APIC_INTERRUPT_COMMAND_LOW;
159        break;
160      case 0x310:
161        regNum = APIC_INTERRUPT_COMMAND_HIGH;
162        break;
163      case 0x320:
164        regNum = APIC_LVT_TIMER;
165        break;
166      case 0x330:
167        regNum = APIC_LVT_THERMAL_SENSOR;
168        break;
169      case 0x340:
170        regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
171        break;
172      case 0x350:
173        regNum = APIC_LVT_LINT0;
174        break;
175      case 0x360:
176        regNum = APIC_LVT_LINT1;
177        break;
178      case 0x370:
179        regNum = APIC_LVT_ERROR;
180        break;
181      case 0x380:
182        regNum = APIC_INITIAL_COUNT;
183        break;
184      case 0x390:
185        regNum = APIC_CURRENT_COUNT;
186        break;
187      case 0x3E0:
188        regNum = APIC_DIVIDE_CONFIGURATION;
189        break;
190      default:
191        // A reserved register field.
192        panic("Accessed reserved register field %#x.\n", paddr);
193        break;
194    }
195    return regNum;
196}
197}
198
199Tick
200X86ISA::Interrupts::read(PacketPtr pkt)
201{
202    Addr offset = pkt->getAddr() - pioAddr;
203    //Make sure we're at least only accessing one register.
204    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
205        panic("Accessed more than one register at a time in the APIC!\n");
206    ApicRegIndex reg = decodeAddr(offset);
207    uint32_t val = htog(readReg(reg));
208    DPRINTF(LocalApic,
209            "Reading Local APIC register %d at offset %#x as %#x.\n",
210            reg, offset, val);
211    pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
212    pkt->makeAtomicResponse();
213    return latency;
214}
215
216Tick
217X86ISA::Interrupts::write(PacketPtr pkt)
218{
219    Addr offset = pkt->getAddr() - pioAddr;
220    //Make sure we're at least only accessing one register.
221    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
222        panic("Accessed more than one register at a time in the APIC!\n");
223    ApicRegIndex reg = decodeAddr(offset);
224    uint32_t val = regs[reg];
225    pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
226    DPRINTF(LocalApic,
227            "Writing Local APIC register %d at offset %#x as %#x.\n",
228            reg, offset, gtoh(val));
229    setReg(reg, gtoh(val));
230    pkt->makeAtomicResponse();
231    return latency;
232}
233void
234X86ISA::Interrupts::requestInterrupt(uint8_t vector,
235        uint8_t deliveryMode, bool level)
236{
237    /*
238     * Fixed and lowest-priority delivery mode interrupts are handled
239     * using the IRR/ISR registers, checking against the TPR, etc.
240     * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
241     */
242    if (deliveryMode == DeliveryMode::Fixed ||
243            deliveryMode == DeliveryMode::LowestPriority) {
244        DPRINTF(LocalApic, "Interrupt is an %s.\n",
245                DeliveryMode::names[deliveryMode]);
246        // Queue up the interrupt in the IRR.
247        if (vector > IRRV)
248            IRRV = vector;
249        if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
250            setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
251            if (level) {
252                setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
253            } else {
254                clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
255            }
256        }
257    } else if (!DeliveryMode::isReserved(deliveryMode)) {
258        DPRINTF(LocalApic, "Interrupt is an %s.\n",
259                DeliveryMode::names[deliveryMode]);
260        if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
261            pendingUnmaskableInt = pendingSmi = true;
262            smiVector = vector;
263        } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
264            pendingUnmaskableInt = pendingNmi = true;
265            nmiVector = vector;
266        } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
267            pendingExtInt = true;
268            extIntVector = vector;
269        } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
270            pendingUnmaskableInt = pendingInit = true;
271            initVector = vector;
272        } else if (deliveryMode == DeliveryMode::SIPI &&
273                !pendingStartup && !startedUp) {
274            pendingUnmaskableInt = pendingStartup = true;
275            startupVector = vector;
276        }
277    }
278#if FULL_SYSTEM //XXX CPU has no wakeup method in SE mode.
279    cpu->wakeup();
280#endif
281}
282
283
284void
285X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
286{
287    assert(newCPU);
288    if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
289        panic("Local APICs can't be moved between CPUs"
290                " with different IDs.\n");
291    }
292    cpu = newCPU;
293    initialApicId = cpu->cpuId();
294    regs[APIC_ID] = (initialApicId << 24);
295}
296
297
298void
299X86ISA::Interrupts::init()
300{
301    //
302    // The local apic must register its address ranges on both its pio port
303    // via the basicpiodevice(piodevice) init() function and its int port
304    // that it inherited from IntDev.  Note IntDev is not a SimObject itself.
305    //
306    BasicPioDevice::init();
307    IntDev::init();
308}
309
310
311Tick
312X86ISA::Interrupts::recvMessage(PacketPtr pkt)
313{
314    Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
315    assert(pkt->cmd == MemCmd::MessageReq);
316    switch(offset)
317    {
318      case 0:
319        {
320            TriggerIntMessage message = pkt->get<TriggerIntMessage>();
321            DPRINTF(LocalApic,
322                    "Got Trigger Interrupt message with vector %#x.\n",
323                    message.vector);
324
325            requestInterrupt(message.vector,
326                    message.deliveryMode, message.trigger);
327        }
328        break;
329      default:
330        panic("Local apic got unknown interrupt message at offset %#x.\n",
331                offset);
332        break;
333    }
334    pkt->makeAtomicResponse();
335    return latency;
336}
337
338
339Tick
340X86ISA::Interrupts::recvResponse(PacketPtr pkt)
341{
342    assert(!pkt->isError());
343    assert(pkt->cmd == MemCmd::MessageResp);
344    if (--pendingIPIs == 0) {
345        InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
346        // Record that the ICR is now idle.
347        low.deliveryStatus = 0;
348        regs[APIC_INTERRUPT_COMMAND_LOW] = low;
349    }
350    DPRINTF(LocalApic, "ICR is now idle.\n");
351    return 0;
352}
353
354
355void
356X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
357{
358    range_list.clear();
359    Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0),
360                                x86LocalAPICAddress(initialApicId, 0) +
361                                PageBytes);
362    range_list.push_back(range);
363    pioAddr = range.start;
364}
365
366
367void
368X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
369{
370    range_list.clear();
371    range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
372                x86InterruptAddress(initialApicId, 0) +
373                PhysAddrAPICRangeSize));
374}
375
376
377uint32_t
378X86ISA::Interrupts::readReg(ApicRegIndex reg)
379{
380    if (reg >= APIC_TRIGGER_MODE(0) &&
381            reg <= APIC_TRIGGER_MODE(15)) {
382        panic("Local APIC Trigger Mode registers are unimplemented.\n");
383    }
384    switch (reg) {
385      case APIC_ARBITRATION_PRIORITY:
386        panic("Local APIC Arbitration Priority register unimplemented.\n");
387        break;
388      case APIC_PROCESSOR_PRIORITY:
389        panic("Local APIC Processor Priority register unimplemented.\n");
390        break;
391      case APIC_ERROR_STATUS:
392        regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
393        break;
394      case APIC_CURRENT_COUNT:
395        {
396            if (apicTimerEvent.scheduled()) {
397                assert(clock);
398                // Compute how many m5 ticks happen per count.
399                uint64_t ticksPerCount = clock *
400                    divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
401                // Compute how many m5 ticks are left.
402                uint64_t val = apicTimerEvent.when() - curTick();
403                // Turn that into a count.
404                val = (val + ticksPerCount - 1) / ticksPerCount;
405                return val;
406            } else {
407                return 0;
408            }
409        }
410      default:
411        break;
412    }
413    return regs[reg];
414}
415
416void
417X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
418{
419    uint32_t newVal = val;
420    if (reg >= APIC_IN_SERVICE(0) &&
421            reg <= APIC_IN_SERVICE(15)) {
422        panic("Local APIC In-Service registers are unimplemented.\n");
423    }
424    if (reg >= APIC_TRIGGER_MODE(0) &&
425            reg <= APIC_TRIGGER_MODE(15)) {
426        panic("Local APIC Trigger Mode registers are unimplemented.\n");
427    }
428    if (reg >= APIC_INTERRUPT_REQUEST(0) &&
429            reg <= APIC_INTERRUPT_REQUEST(15)) {
430        panic("Local APIC Interrupt Request registers "
431                "are unimplemented.\n");
432    }
433    switch (reg) {
434      case APIC_ID:
435        newVal = val & 0xFF;
436        break;
437      case APIC_VERSION:
438        // The Local APIC Version register is read only.
439        return;
440      case APIC_TASK_PRIORITY:
441        newVal = val & 0xFF;
442        break;
443      case APIC_ARBITRATION_PRIORITY:
444        panic("Local APIC Arbitration Priority register unimplemented.\n");
445        break;
446      case APIC_PROCESSOR_PRIORITY:
447        panic("Local APIC Processor Priority register unimplemented.\n");
448        break;
449      case APIC_EOI:
450        // Remove the interrupt that just completed from the local apic state.
451        clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
452        updateISRV();
453        return;
454      case APIC_LOGICAL_DESTINATION:
455        newVal = val & 0xFF000000;
456        break;
457      case APIC_DESTINATION_FORMAT:
458        newVal = val | 0x0FFFFFFF;
459        break;
460      case APIC_SPURIOUS_INTERRUPT_VECTOR:
461        regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
462        regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
463        if (val & (1 << 9))
464            warn("Focus processor checking not implemented.\n");
465        break;
466      case APIC_ERROR_STATUS:
467        {
468            if (regs[APIC_INTERNAL_STATE] & 0x1) {
469                regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
470                newVal = 0;
471            } else {
472                regs[APIC_INTERNAL_STATE] |= ULL(0x1);
473                return;
474            }
475
476        }
477        break;
478      case APIC_INTERRUPT_COMMAND_LOW:
479        {
480            InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
481            // Check if we're already sending an IPI.
482            if (low.deliveryStatus) {
483                newVal = low;
484                break;
485            }
486            low = val;
487            InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
488            // Record that an IPI is being sent.
489            low.deliveryStatus = 1;
490            TriggerIntMessage message = 0;
491            message.destination = high.destination;
492            message.vector = low.vector;
493            message.deliveryMode = low.deliveryMode;
494            message.destMode = low.destMode;
495            message.level = low.level;
496            message.trigger = low.trigger;
497            bool timing = sys->getMemoryMode() == Enums::timing;
498            // Be careful no updates of the delivery status bit get lost.
499            regs[APIC_INTERRUPT_COMMAND_LOW] = low;
500            ApicList apics;
501            int numContexts = sys->numContexts();
502            switch (low.destShorthand) {
503              case 0:
504                if (message.deliveryMode == DeliveryMode::LowestPriority) {
505                    panic("Lowest priority delivery mode "
506                            "IPIs aren't implemented.\n");
507                }
508                if (message.destMode == 1) {
509                    int dest = message.destination;
510                    hack_once("Assuming logical destinations are 1 << id.\n");
511                    for (int i = 0; i < numContexts; i++) {
512                        if (dest & 0x1)
513                            apics.push_back(i);
514                        dest = dest >> 1;
515                    }
516                } else {
517                    if (message.destination == 0xFF) {
518                        for (int i = 0; i < numContexts; i++) {
519                            if (i == initialApicId) {
520                                requestInterrupt(message.vector,
521                                        message.deliveryMode, message.trigger);
522                            } else {
523                                apics.push_back(i);
524                            }
525                        }
526                    } else {
527                        if (message.destination == initialApicId) {
528                            requestInterrupt(message.vector,
529                                    message.deliveryMode, message.trigger);
530                        } else {
531                            apics.push_back(message.destination);
532                        }
533                    }
534                }
535                break;
536              case 1:
537                newVal = val;
538                requestInterrupt(message.vector,
539                        message.deliveryMode, message.trigger);
540                break;
541              case 2:
542                requestInterrupt(message.vector,
543                        message.deliveryMode, message.trigger);
544                // Fall through
545              case 3:
546                {
547                    for (int i = 0; i < numContexts; i++) {
548                        if (i != initialApicId) {
549                            apics.push_back(i);
550                        }
551                    }
552                }
553                break;
554            }
555            pendingIPIs += apics.size();
556            intPort->sendMessage(apics, message, timing);
557            newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
558        }
559        break;
560      case APIC_LVT_TIMER:
561      case APIC_LVT_THERMAL_SENSOR:
562      case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
563      case APIC_LVT_LINT0:
564      case APIC_LVT_LINT1:
565      case APIC_LVT_ERROR:
566        {
567            uint64_t readOnlyMask = (1 << 12) | (1 << 14);
568            newVal = (val & ~readOnlyMask) |
569                     (regs[reg] & readOnlyMask);
570        }
571        break;
572      case APIC_INITIAL_COUNT:
573        {
574            assert(clock);
575            newVal = bits(val, 31, 0);
576            // Compute how many timer ticks we're being programmed for.
577            uint64_t newCount = newVal *
578                (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
579            // Schedule on the edge of the next tick plus the new count.
580            Tick offset = curTick() % clock;
581            if (offset) {
582                reschedule(apicTimerEvent,
583                        curTick() + (newCount + 1) * clock - offset, true);
584            } else {
585                reschedule(apicTimerEvent,
586                        curTick() + newCount * clock, true);
587            }
588        }
589        break;
590      case APIC_CURRENT_COUNT:
591        //Local APIC Current Count register is read only.
592        return;
593      case APIC_DIVIDE_CONFIGURATION:
594        newVal = val & 0xB;
595        break;
596      default:
597        break;
598    }
599    regs[reg] = newVal;
600    return;
601}
602
603
604X86ISA::Interrupts::Interrupts(Params * p) :
605    BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
606    clock(0),
607    apicTimerEvent(this),
608    pendingSmi(false), smiVector(0),
609    pendingNmi(false), nmiVector(0),
610    pendingExtInt(false), extIntVector(0),
611    pendingInit(false), initVector(0),
612    pendingStartup(false), startupVector(0),
613    startedUp(false), pendingUnmaskableInt(false),
614    pendingIPIs(0), cpu(NULL)
615{
616    pioSize = PageBytes;
617    memset(regs, 0, sizeof(regs));
618    //Set the local apic DFR to the flat model.
619    regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
620    ISRV = 0;
621    IRRV = 0;
622}
623
624
625bool
626X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
627{
628    RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
629    if (pendingUnmaskableInt) {
630        DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
631        return true;
632    }
633    if (rflags.intf) {
634        if (pendingExtInt) {
635            DPRINTF(LocalApic, "Reported pending external interrupt.\n");
636            return true;
637        }
638        if (IRRV > ISRV && bits(IRRV, 7, 4) >
639               bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
640            DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
641            return true;
642        }
643    }
644    return false;
645}
646
647Fault
648X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
649{
650    assert(checkInterrupts(tc));
651    // These are all probably fairly uncommon, so we'll make them easier to
652    // check for.
653    if (pendingUnmaskableInt) {
654        if (pendingSmi) {
655            DPRINTF(LocalApic, "Generated SMI fault object.\n");
656            return new SystemManagementInterrupt();
657        } else if (pendingNmi) {
658            DPRINTF(LocalApic, "Generated NMI fault object.\n");
659            return new NonMaskableInterrupt(nmiVector);
660        } else if (pendingInit) {
661            DPRINTF(LocalApic, "Generated INIT fault object.\n");
662            return new InitInterrupt(initVector);
663        } else if (pendingStartup) {
664            DPRINTF(LocalApic, "Generating SIPI fault object.\n");
665            return new StartupInterrupt(startupVector);
666        } else {
667            panic("pendingUnmaskableInt set, but no unmaskable "
668                    "ints were pending.\n");
669            return NoFault;
670        }
671    } else if (pendingExtInt) {
672        DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
673        return new ExternalInterrupt(extIntVector);
674    } else {
675        DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
676        // The only thing left are fixed and lowest priority interrupts.
677        return new ExternalInterrupt(IRRV);
678    }
679}
680
681void
682X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
683{
684    assert(checkInterrupts(tc));
685    if (pendingUnmaskableInt) {
686        if (pendingSmi) {
687            DPRINTF(LocalApic, "SMI sent to core.\n");
688            pendingSmi = false;
689        } else if (pendingNmi) {
690            DPRINTF(LocalApic, "NMI sent to core.\n");
691            pendingNmi = false;
692        } else if (pendingInit) {
693            DPRINTF(LocalApic, "Init sent to core.\n");
694            pendingInit = false;
695            startedUp = false;
696        } else if (pendingStartup) {
697            DPRINTF(LocalApic, "SIPI sent to core.\n");
698            pendingStartup = false;
699            startedUp = true;
700        }
701        if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
702            pendingUnmaskableInt = false;
703    } else if (pendingExtInt) {
704        pendingExtInt = false;
705    } else {
706        DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
707        // Mark the interrupt as "in service".
708        ISRV = IRRV;
709        setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
710        // Clear it out of the IRR.
711        clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
712        updateIRRV();
713    }
714}
715
716void
717X86ISA::Interrupts::serialize(std::ostream &os)
718{
719    SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
720    SERIALIZE_SCALAR(clock);
721    SERIALIZE_SCALAR(pendingSmi);
722    SERIALIZE_SCALAR(smiVector);
723    SERIALIZE_SCALAR(pendingNmi);
724    SERIALIZE_SCALAR(nmiVector);
725    SERIALIZE_SCALAR(pendingExtInt);
726    SERIALIZE_SCALAR(extIntVector);
727    SERIALIZE_SCALAR(pendingInit);
728    SERIALIZE_SCALAR(initVector);
729    SERIALIZE_SCALAR(pendingStartup);
730    SERIALIZE_SCALAR(startupVector);
731    SERIALIZE_SCALAR(startedUp);
732    SERIALIZE_SCALAR(pendingUnmaskableInt);
733    SERIALIZE_SCALAR(pendingIPIs);
734    SERIALIZE_SCALAR(IRRV);
735    SERIALIZE_SCALAR(ISRV);
736    bool apicTimerEventScheduled = apicTimerEvent.scheduled();
737    SERIALIZE_SCALAR(apicTimerEventScheduled);
738    Tick apicTimerEventTick = apicTimerEvent.when();
739    SERIALIZE_SCALAR(apicTimerEventTick);
740}
741
742void
743X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string &section)
744{
745    UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
746    UNSERIALIZE_SCALAR(clock);
747    UNSERIALIZE_SCALAR(pendingSmi);
748    UNSERIALIZE_SCALAR(smiVector);
749    UNSERIALIZE_SCALAR(pendingNmi);
750    UNSERIALIZE_SCALAR(nmiVector);
751    UNSERIALIZE_SCALAR(pendingExtInt);
752    UNSERIALIZE_SCALAR(extIntVector);
753    UNSERIALIZE_SCALAR(pendingInit);
754    UNSERIALIZE_SCALAR(initVector);
755    UNSERIALIZE_SCALAR(pendingStartup);
756    UNSERIALIZE_SCALAR(startupVector);
757    UNSERIALIZE_SCALAR(startedUp);
758    UNSERIALIZE_SCALAR(pendingUnmaskableInt);
759    UNSERIALIZE_SCALAR(pendingIPIs);
760    UNSERIALIZE_SCALAR(IRRV);
761    UNSERIALIZE_SCALAR(ISRV);
762    bool apicTimerEventScheduled;
763    UNSERIALIZE_SCALAR(apicTimerEventScheduled);
764    if (apicTimerEventScheduled) {
765        Tick apicTimerEventTick;
766        UNSERIALIZE_SCALAR(apicTimerEventTick);
767        if (apicTimerEvent.scheduled()) {
768            reschedule(apicTimerEvent, apicTimerEventTick, true);
769        } else {
770            schedule(apicTimerEvent, apicTimerEventTick);
771        }
772    }
773}
774
775X86ISA::Interrupts *
776X86LocalApicParams::create()
777{
778    return new X86ISA::Interrupts(this);
779}
780