interrupts.cc revision 8746:42d3554b1c35
1/* 2 * Copyright (c) 2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include "arch/x86/regs/apic.hh" 41#include "arch/x86/interrupts.hh" 42#include "arch/x86/intmessage.hh" 43#include "cpu/base.hh" 44#include "debug/LocalApic.hh" 45#include "dev/x86/i82094aa.hh" 46#include "dev/x86/pc.hh" 47#include "dev/x86/south_bridge.hh" 48#include "mem/packet_access.hh" 49#include "sim/system.hh" 50 51int 52divideFromConf(uint32_t conf) 53{ 54 // This figures out what division we want from the division configuration 55 // register in the local APIC. The encoding is a little odd but it can 56 // be deciphered fairly easily. 57 int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 58 shift = (shift + 1) % 8; 59 return 1 << shift; 60} 61 62namespace X86ISA 63{ 64 65ApicRegIndex 66decodeAddr(Addr paddr) 67{ 68 ApicRegIndex regNum; 69 paddr &= ~mask(3); 70 switch (paddr) 71 { 72 case 0x20: 73 regNum = APIC_ID; 74 break; 75 case 0x30: 76 regNum = APIC_VERSION; 77 break; 78 case 0x80: 79 regNum = APIC_TASK_PRIORITY; 80 break; 81 case 0x90: 82 regNum = APIC_ARBITRATION_PRIORITY; 83 break; 84 case 0xA0: 85 regNum = APIC_PROCESSOR_PRIORITY; 86 break; 87 case 0xB0: 88 regNum = APIC_EOI; 89 break; 90 case 0xD0: 91 regNum = APIC_LOGICAL_DESTINATION; 92 break; 93 case 0xE0: 94 regNum = APIC_DESTINATION_FORMAT; 95 break; 96 case 0xF0: 97 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 98 break; 99 case 0x100: 100 case 0x108: 101 case 0x110: 102 case 0x118: 103 case 0x120: 104 case 0x128: 105 case 0x130: 106 case 0x138: 107 case 0x140: 108 case 0x148: 109 case 0x150: 110 case 0x158: 111 case 0x160: 112 case 0x168: 113 case 0x170: 114 case 0x178: 115 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 116 break; 117 case 0x180: 118 case 0x188: 119 case 0x190: 120 case 0x198: 121 case 0x1A0: 122 case 0x1A8: 123 case 0x1B0: 124 case 0x1B8: 125 case 0x1C0: 126 case 0x1C8: 127 case 0x1D0: 128 case 0x1D8: 129 case 0x1E0: 130 case 0x1E8: 131 case 0x1F0: 132 case 0x1F8: 133 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 134 break; 135 case 0x200: 136 case 0x208: 137 case 0x210: 138 case 0x218: 139 case 0x220: 140 case 0x228: 141 case 0x230: 142 case 0x238: 143 case 0x240: 144 case 0x248: 145 case 0x250: 146 case 0x258: 147 case 0x260: 148 case 0x268: 149 case 0x270: 150 case 0x278: 151 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 152 break; 153 case 0x280: 154 regNum = APIC_ERROR_STATUS; 155 break; 156 case 0x300: 157 regNum = APIC_INTERRUPT_COMMAND_LOW; 158 break; 159 case 0x310: 160 regNum = APIC_INTERRUPT_COMMAND_HIGH; 161 break; 162 case 0x320: 163 regNum = APIC_LVT_TIMER; 164 break; 165 case 0x330: 166 regNum = APIC_LVT_THERMAL_SENSOR; 167 break; 168 case 0x340: 169 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 170 break; 171 case 0x350: 172 regNum = APIC_LVT_LINT0; 173 break; 174 case 0x360: 175 regNum = APIC_LVT_LINT1; 176 break; 177 case 0x370: 178 regNum = APIC_LVT_ERROR; 179 break; 180 case 0x380: 181 regNum = APIC_INITIAL_COUNT; 182 break; 183 case 0x390: 184 regNum = APIC_CURRENT_COUNT; 185 break; 186 case 0x3E0: 187 regNum = APIC_DIVIDE_CONFIGURATION; 188 break; 189 default: 190 // A reserved register field. 191 panic("Accessed reserved register field %#x.\n", paddr); 192 break; 193 } 194 return regNum; 195} 196} 197 198Tick 199X86ISA::Interrupts::read(PacketPtr pkt) 200{ 201 Addr offset = pkt->getAddr() - pioAddr; 202 //Make sure we're at least only accessing one register. 203 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 204 panic("Accessed more than one register at a time in the APIC!\n"); 205 ApicRegIndex reg = decodeAddr(offset); 206 uint32_t val = htog(readReg(reg)); 207 DPRINTF(LocalApic, 208 "Reading Local APIC register %d at offset %#x as %#x.\n", 209 reg, offset, val); 210 pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 211 pkt->makeAtomicResponse(); 212 return latency; 213} 214 215Tick 216X86ISA::Interrupts::write(PacketPtr pkt) 217{ 218 Addr offset = pkt->getAddr() - pioAddr; 219 //Make sure we're at least only accessing one register. 220 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 221 panic("Accessed more than one register at a time in the APIC!\n"); 222 ApicRegIndex reg = decodeAddr(offset); 223 uint32_t val = regs[reg]; 224 pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 225 DPRINTF(LocalApic, 226 "Writing Local APIC register %d at offset %#x as %#x.\n", 227 reg, offset, gtoh(val)); 228 setReg(reg, gtoh(val)); 229 pkt->makeAtomicResponse(); 230 return latency; 231} 232void 233X86ISA::Interrupts::requestInterrupt(uint8_t vector, 234 uint8_t deliveryMode, bool level) 235{ 236 /* 237 * Fixed and lowest-priority delivery mode interrupts are handled 238 * using the IRR/ISR registers, checking against the TPR, etc. 239 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 240 */ 241 if (deliveryMode == DeliveryMode::Fixed || 242 deliveryMode == DeliveryMode::LowestPriority) { 243 DPRINTF(LocalApic, "Interrupt is an %s.\n", 244 DeliveryMode::names[deliveryMode]); 245 // Queue up the interrupt in the IRR. 246 if (vector > IRRV) 247 IRRV = vector; 248 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 249 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 250 if (level) { 251 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 252 } else { 253 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 254 } 255 } 256 } else if (!DeliveryMode::isReserved(deliveryMode)) { 257 DPRINTF(LocalApic, "Interrupt is an %s.\n", 258 DeliveryMode::names[deliveryMode]); 259 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 260 pendingUnmaskableInt = pendingSmi = true; 261 smiVector = vector; 262 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 263 pendingUnmaskableInt = pendingNmi = true; 264 nmiVector = vector; 265 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 266 pendingExtInt = true; 267 extIntVector = vector; 268 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 269 pendingUnmaskableInt = pendingInit = true; 270 initVector = vector; 271 } else if (deliveryMode == DeliveryMode::SIPI && 272 !pendingStartup && !startedUp) { 273 pendingUnmaskableInt = pendingStartup = true; 274 startupVector = vector; 275 } 276 } 277#if FULL_SYSTEM //XXX CPU has no wakeup method in SE mode. 278 cpu->wakeup(); 279#endif 280} 281 282 283void 284X86ISA::Interrupts::setCPU(BaseCPU * newCPU) 285{ 286 assert(newCPU); 287 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 288 panic("Local APICs can't be moved between CPUs" 289 " with different IDs.\n"); 290 } 291 cpu = newCPU; 292 initialApicId = cpu->cpuId(); 293 regs[APIC_ID] = (initialApicId << 24); 294} 295 296 297void 298X86ISA::Interrupts::init() 299{ 300 // 301 // The local apic must register its address ranges on both its pio port 302 // via the basicpiodevice(piodevice) init() function and its int port 303 // that it inherited from IntDev. Note IntDev is not a SimObject itself. 304 // 305 BasicPioDevice::init(); 306 IntDev::init(); 307} 308 309 310Tick 311X86ISA::Interrupts::recvMessage(PacketPtr pkt) 312{ 313 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 314 assert(pkt->cmd == MemCmd::MessageReq); 315 switch(offset) 316 { 317 case 0: 318 { 319 TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 320 DPRINTF(LocalApic, 321 "Got Trigger Interrupt message with vector %#x.\n", 322 message.vector); 323 324 requestInterrupt(message.vector, 325 message.deliveryMode, message.trigger); 326 } 327 break; 328 default: 329 panic("Local apic got unknown interrupt message at offset %#x.\n", 330 offset); 331 break; 332 } 333 pkt->makeAtomicResponse(); 334 return latency; 335} 336 337 338Tick 339X86ISA::Interrupts::recvResponse(PacketPtr pkt) 340{ 341 assert(!pkt->isError()); 342 assert(pkt->cmd == MemCmd::MessageResp); 343 if (--pendingIPIs == 0) { 344 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 345 // Record that the ICR is now idle. 346 low.deliveryStatus = 0; 347 regs[APIC_INTERRUPT_COMMAND_LOW] = low; 348 } 349 DPRINTF(LocalApic, "ICR is now idle.\n"); 350 return 0; 351} 352 353 354void 355X86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 356{ 357 range_list.clear(); 358 Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0), 359 x86LocalAPICAddress(initialApicId, 0) + 360 PageBytes); 361 range_list.push_back(range); 362 pioAddr = range.start; 363} 364 365 366void 367X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 368{ 369 range_list.clear(); 370 range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 371 x86InterruptAddress(initialApicId, 0) + 372 PhysAddrAPICRangeSize)); 373} 374 375 376uint32_t 377X86ISA::Interrupts::readReg(ApicRegIndex reg) 378{ 379 if (reg >= APIC_TRIGGER_MODE(0) && 380 reg <= APIC_TRIGGER_MODE(15)) { 381 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 382 } 383 switch (reg) { 384 case APIC_ARBITRATION_PRIORITY: 385 panic("Local APIC Arbitration Priority register unimplemented.\n"); 386 break; 387 case APIC_PROCESSOR_PRIORITY: 388 panic("Local APIC Processor Priority register unimplemented.\n"); 389 break; 390 case APIC_ERROR_STATUS: 391 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 392 break; 393 case APIC_CURRENT_COUNT: 394 { 395 if (apicTimerEvent.scheduled()) { 396 assert(clock); 397 // Compute how many m5 ticks happen per count. 398 uint64_t ticksPerCount = clock * 399 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 400 // Compute how many m5 ticks are left. 401 uint64_t val = apicTimerEvent.when() - curTick(); 402 // Turn that into a count. 403 val = (val + ticksPerCount - 1) / ticksPerCount; 404 return val; 405 } else { 406 return 0; 407 } 408 } 409 default: 410 break; 411 } 412 return regs[reg]; 413} 414 415void 416X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 417{ 418 uint32_t newVal = val; 419 if (reg >= APIC_IN_SERVICE(0) && 420 reg <= APIC_IN_SERVICE(15)) { 421 panic("Local APIC In-Service registers are unimplemented.\n"); 422 } 423 if (reg >= APIC_TRIGGER_MODE(0) && 424 reg <= APIC_TRIGGER_MODE(15)) { 425 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 426 } 427 if (reg >= APIC_INTERRUPT_REQUEST(0) && 428 reg <= APIC_INTERRUPT_REQUEST(15)) { 429 panic("Local APIC Interrupt Request registers " 430 "are unimplemented.\n"); 431 } 432 switch (reg) { 433 case APIC_ID: 434 newVal = val & 0xFF; 435 break; 436 case APIC_VERSION: 437 // The Local APIC Version register is read only. 438 return; 439 case APIC_TASK_PRIORITY: 440 newVal = val & 0xFF; 441 break; 442 case APIC_ARBITRATION_PRIORITY: 443 panic("Local APIC Arbitration Priority register unimplemented.\n"); 444 break; 445 case APIC_PROCESSOR_PRIORITY: 446 panic("Local APIC Processor Priority register unimplemented.\n"); 447 break; 448 case APIC_EOI: 449 // Remove the interrupt that just completed from the local apic state. 450 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 451 updateISRV(); 452 return; 453 case APIC_LOGICAL_DESTINATION: 454 newVal = val & 0xFF000000; 455 break; 456 case APIC_DESTINATION_FORMAT: 457 newVal = val | 0x0FFFFFFF; 458 break; 459 case APIC_SPURIOUS_INTERRUPT_VECTOR: 460 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 461 regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 462 if (val & (1 << 9)) 463 warn("Focus processor checking not implemented.\n"); 464 break; 465 case APIC_ERROR_STATUS: 466 { 467 if (regs[APIC_INTERNAL_STATE] & 0x1) { 468 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 469 newVal = 0; 470 } else { 471 regs[APIC_INTERNAL_STATE] |= ULL(0x1); 472 return; 473 } 474 475 } 476 break; 477 case APIC_INTERRUPT_COMMAND_LOW: 478 { 479 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 480 // Check if we're already sending an IPI. 481 if (low.deliveryStatus) { 482 newVal = low; 483 break; 484 } 485 low = val; 486 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 487 // Record that an IPI is being sent. 488 low.deliveryStatus = 1; 489 TriggerIntMessage message = 0; 490 message.destination = high.destination; 491 message.vector = low.vector; 492 message.deliveryMode = low.deliveryMode; 493 message.destMode = low.destMode; 494 message.level = low.level; 495 message.trigger = low.trigger; 496 bool timing = sys->getMemoryMode() == Enums::timing; 497 // Be careful no updates of the delivery status bit get lost. 498 regs[APIC_INTERRUPT_COMMAND_LOW] = low; 499 ApicList apics; 500 int numContexts = sys->numContexts(); 501 switch (low.destShorthand) { 502 case 0: 503 if (message.deliveryMode == DeliveryMode::LowestPriority) { 504 panic("Lowest priority delivery mode " 505 "IPIs aren't implemented.\n"); 506 } 507 if (message.destMode == 1) { 508 int dest = message.destination; 509 hack_once("Assuming logical destinations are 1 << id.\n"); 510 for (int i = 0; i < numContexts; i++) { 511 if (dest & 0x1) 512 apics.push_back(i); 513 dest = dest >> 1; 514 } 515 } else { 516 if (message.destination == 0xFF) { 517 for (int i = 0; i < numContexts; i++) { 518 if (i == initialApicId) { 519 requestInterrupt(message.vector, 520 message.deliveryMode, message.trigger); 521 } else { 522 apics.push_back(i); 523 } 524 } 525 } else { 526 if (message.destination == initialApicId) { 527 requestInterrupt(message.vector, 528 message.deliveryMode, message.trigger); 529 } else { 530 apics.push_back(message.destination); 531 } 532 } 533 } 534 break; 535 case 1: 536 newVal = val; 537 requestInterrupt(message.vector, 538 message.deliveryMode, message.trigger); 539 break; 540 case 2: 541 requestInterrupt(message.vector, 542 message.deliveryMode, message.trigger); 543 // Fall through 544 case 3: 545 { 546 for (int i = 0; i < numContexts; i++) { 547 if (i != initialApicId) { 548 apics.push_back(i); 549 } 550 } 551 } 552 break; 553 } 554 pendingIPIs += apics.size(); 555 intPort->sendMessage(apics, message, timing); 556 newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 557 } 558 break; 559 case APIC_LVT_TIMER: 560 case APIC_LVT_THERMAL_SENSOR: 561 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 562 case APIC_LVT_LINT0: 563 case APIC_LVT_LINT1: 564 case APIC_LVT_ERROR: 565 { 566 uint64_t readOnlyMask = (1 << 12) | (1 << 14); 567 newVal = (val & ~readOnlyMask) | 568 (regs[reg] & readOnlyMask); 569 } 570 break; 571 case APIC_INITIAL_COUNT: 572 { 573 assert(clock); 574 newVal = bits(val, 31, 0); 575 // Compute how many timer ticks we're being programmed for. 576 uint64_t newCount = newVal * 577 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 578 // Schedule on the edge of the next tick plus the new count. 579 Tick offset = curTick() % clock; 580 if (offset) { 581 reschedule(apicTimerEvent, 582 curTick() + (newCount + 1) * clock - offset, true); 583 } else { 584 reschedule(apicTimerEvent, 585 curTick() + newCount * clock, true); 586 } 587 } 588 break; 589 case APIC_CURRENT_COUNT: 590 //Local APIC Current Count register is read only. 591 return; 592 case APIC_DIVIDE_CONFIGURATION: 593 newVal = val & 0xB; 594 break; 595 default: 596 break; 597 } 598 regs[reg] = newVal; 599 return; 600} 601 602 603X86ISA::Interrupts::Interrupts(Params * p) : 604 BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency), 605 clock(0), 606 apicTimerEvent(this), 607 pendingSmi(false), smiVector(0), 608 pendingNmi(false), nmiVector(0), 609 pendingExtInt(false), extIntVector(0), 610 pendingInit(false), initVector(0), 611 pendingStartup(false), startupVector(0), 612 startedUp(false), pendingUnmaskableInt(false), 613 pendingIPIs(0), cpu(NULL) 614{ 615 pioSize = PageBytes; 616 memset(regs, 0, sizeof(regs)); 617 //Set the local apic DFR to the flat model. 618 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 619 ISRV = 0; 620 IRRV = 0; 621} 622 623 624bool 625X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 626{ 627 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 628 if (pendingUnmaskableInt) { 629 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 630 return true; 631 } 632 if (rflags.intf) { 633 if (pendingExtInt) { 634 DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 635 return true; 636 } 637 if (IRRV > ISRV && bits(IRRV, 7, 4) > 638 bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 639 DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 640 return true; 641 } 642 } 643 return false; 644} 645 646Fault 647X86ISA::Interrupts::getInterrupt(ThreadContext *tc) 648{ 649 assert(checkInterrupts(tc)); 650 // These are all probably fairly uncommon, so we'll make them easier to 651 // check for. 652 if (pendingUnmaskableInt) { 653 if (pendingSmi) { 654 DPRINTF(LocalApic, "Generated SMI fault object.\n"); 655 return new SystemManagementInterrupt(); 656 } else if (pendingNmi) { 657 DPRINTF(LocalApic, "Generated NMI fault object.\n"); 658 return new NonMaskableInterrupt(nmiVector); 659 } else if (pendingInit) { 660 DPRINTF(LocalApic, "Generated INIT fault object.\n"); 661 return new InitInterrupt(initVector); 662 } else if (pendingStartup) { 663 DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 664 return new StartupInterrupt(startupVector); 665 } else { 666 panic("pendingUnmaskableInt set, but no unmaskable " 667 "ints were pending.\n"); 668 return NoFault; 669 } 670 } else if (pendingExtInt) { 671 DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 672 return new ExternalInterrupt(extIntVector); 673 } else { 674 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 675 // The only thing left are fixed and lowest priority interrupts. 676 return new ExternalInterrupt(IRRV); 677 } 678} 679 680void 681X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 682{ 683 assert(checkInterrupts(tc)); 684 if (pendingUnmaskableInt) { 685 if (pendingSmi) { 686 DPRINTF(LocalApic, "SMI sent to core.\n"); 687 pendingSmi = false; 688 } else if (pendingNmi) { 689 DPRINTF(LocalApic, "NMI sent to core.\n"); 690 pendingNmi = false; 691 } else if (pendingInit) { 692 DPRINTF(LocalApic, "Init sent to core.\n"); 693 pendingInit = false; 694 startedUp = false; 695 } else if (pendingStartup) { 696 DPRINTF(LocalApic, "SIPI sent to core.\n"); 697 pendingStartup = false; 698 startedUp = true; 699 } 700 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 701 pendingUnmaskableInt = false; 702 } else if (pendingExtInt) { 703 pendingExtInt = false; 704 } else { 705 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 706 // Mark the interrupt as "in service". 707 ISRV = IRRV; 708 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 709 // Clear it out of the IRR. 710 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 711 updateIRRV(); 712 } 713} 714 715void 716X86ISA::Interrupts::serialize(std::ostream &os) 717{ 718 SERIALIZE_ARRAY(regs, NUM_APIC_REGS); 719 SERIALIZE_SCALAR(clock); 720 SERIALIZE_SCALAR(pendingSmi); 721 SERIALIZE_SCALAR(smiVector); 722 SERIALIZE_SCALAR(pendingNmi); 723 SERIALIZE_SCALAR(nmiVector); 724 SERIALIZE_SCALAR(pendingExtInt); 725 SERIALIZE_SCALAR(extIntVector); 726 SERIALIZE_SCALAR(pendingInit); 727 SERIALIZE_SCALAR(initVector); 728 SERIALIZE_SCALAR(pendingStartup); 729 SERIALIZE_SCALAR(startupVector); 730 SERIALIZE_SCALAR(startedUp); 731 SERIALIZE_SCALAR(pendingUnmaskableInt); 732 SERIALIZE_SCALAR(pendingIPIs); 733 SERIALIZE_SCALAR(IRRV); 734 SERIALIZE_SCALAR(ISRV); 735 bool apicTimerEventScheduled = apicTimerEvent.scheduled(); 736 SERIALIZE_SCALAR(apicTimerEventScheduled); 737 Tick apicTimerEventTick = apicTimerEvent.when(); 738 SERIALIZE_SCALAR(apicTimerEventTick); 739} 740 741void 742X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion) 743{ 744 UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS); 745 UNSERIALIZE_SCALAR(clock); 746 UNSERIALIZE_SCALAR(pendingSmi); 747 UNSERIALIZE_SCALAR(smiVector); 748 UNSERIALIZE_SCALAR(pendingNmi); 749 UNSERIALIZE_SCALAR(nmiVector); 750 UNSERIALIZE_SCALAR(pendingExtInt); 751 UNSERIALIZE_SCALAR(extIntVector); 752 UNSERIALIZE_SCALAR(pendingInit); 753 UNSERIALIZE_SCALAR(initVector); 754 UNSERIALIZE_SCALAR(pendingStartup); 755 UNSERIALIZE_SCALAR(startupVector); 756 UNSERIALIZE_SCALAR(startedUp); 757 UNSERIALIZE_SCALAR(pendingUnmaskableInt); 758 UNSERIALIZE_SCALAR(pendingIPIs); 759 UNSERIALIZE_SCALAR(IRRV); 760 UNSERIALIZE_SCALAR(ISRV); 761 bool apicTimerEventScheduled; 762 UNSERIALIZE_SCALAR(apicTimerEventScheduled); 763 if (apicTimerEventScheduled) { 764 Tick apicTimerEventTick; 765 UNSERIALIZE_SCALAR(apicTimerEventTick); 766 if (apicTimerEvent.scheduled()) { 767 reschedule(apicTimerEvent, apicTimerEventTick, true); 768 } else { 769 schedule(apicTimerEvent, apicTimerEventTick); 770 } 771 } 772} 773 774X86ISA::Interrupts * 775X86LocalApicParams::create() 776{ 777 return new X86ISA::Interrupts(this); 778} 779