interrupts.cc revision 8232
1/* 2 * Copyright (c) 2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include "arch/x86/regs/apic.hh" 41#include "arch/x86/interrupts.hh" 42#include "arch/x86/intmessage.hh" 43#include "cpu/base.hh" 44#include "debug/LocalApic.hh" 45#include "dev/x86/i82094aa.hh" 46#include "dev/x86/pc.hh" 47#include "dev/x86/south_bridge.hh" 48#include "mem/packet_access.hh" 49#include "sim/system.hh" 50 51int 52divideFromConf(uint32_t conf) 53{ 54 // This figures out what division we want from the division configuration 55 // register in the local APIC. The encoding is a little odd but it can 56 // be deciphered fairly easily. 57 int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 58 shift = (shift + 1) % 8; 59 return 1 << shift; 60} 61 62namespace X86ISA 63{ 64 65ApicRegIndex 66decodeAddr(Addr paddr) 67{ 68 ApicRegIndex regNum; 69 paddr &= ~mask(3); 70 switch (paddr) 71 { 72 case 0x20: 73 regNum = APIC_ID; 74 break; 75 case 0x30: 76 regNum = APIC_VERSION; 77 break; 78 case 0x80: 79 regNum = APIC_TASK_PRIORITY; 80 break; 81 case 0x90: 82 regNum = APIC_ARBITRATION_PRIORITY; 83 break; 84 case 0xA0: 85 regNum = APIC_PROCESSOR_PRIORITY; 86 break; 87 case 0xB0: 88 regNum = APIC_EOI; 89 break; 90 case 0xD0: 91 regNum = APIC_LOGICAL_DESTINATION; 92 break; 93 case 0xE0: 94 regNum = APIC_DESTINATION_FORMAT; 95 break; 96 case 0xF0: 97 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 98 break; 99 case 0x100: 100 case 0x108: 101 case 0x110: 102 case 0x118: 103 case 0x120: 104 case 0x128: 105 case 0x130: 106 case 0x138: 107 case 0x140: 108 case 0x148: 109 case 0x150: 110 case 0x158: 111 case 0x160: 112 case 0x168: 113 case 0x170: 114 case 0x178: 115 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 116 break; 117 case 0x180: 118 case 0x188: 119 case 0x190: 120 case 0x198: 121 case 0x1A0: 122 case 0x1A8: 123 case 0x1B0: 124 case 0x1B8: 125 case 0x1C0: 126 case 0x1C8: 127 case 0x1D0: 128 case 0x1D8: 129 case 0x1E0: 130 case 0x1E8: 131 case 0x1F0: 132 case 0x1F8: 133 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 134 break; 135 case 0x200: 136 case 0x208: 137 case 0x210: 138 case 0x218: 139 case 0x220: 140 case 0x228: 141 case 0x230: 142 case 0x238: 143 case 0x240: 144 case 0x248: 145 case 0x250: 146 case 0x258: 147 case 0x260: 148 case 0x268: 149 case 0x270: 150 case 0x278: 151 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 152 break; 153 case 0x280: 154 regNum = APIC_ERROR_STATUS; 155 break; 156 case 0x300: 157 regNum = APIC_INTERRUPT_COMMAND_LOW; 158 break; 159 case 0x310: 160 regNum = APIC_INTERRUPT_COMMAND_HIGH; 161 break; 162 case 0x320: 163 regNum = APIC_LVT_TIMER; 164 break; 165 case 0x330: 166 regNum = APIC_LVT_THERMAL_SENSOR; 167 break; 168 case 0x340: 169 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 170 break; 171 case 0x350: 172 regNum = APIC_LVT_LINT0; 173 break; 174 case 0x360: 175 regNum = APIC_LVT_LINT1; 176 break; 177 case 0x370: 178 regNum = APIC_LVT_ERROR; 179 break; 180 case 0x380: 181 regNum = APIC_INITIAL_COUNT; 182 break; 183 case 0x390: 184 regNum = APIC_CURRENT_COUNT; 185 break; 186 case 0x3E0: 187 regNum = APIC_DIVIDE_CONFIGURATION; 188 break; 189 default: 190 // A reserved register field. 191 panic("Accessed reserved register field %#x.\n", paddr); 192 break; 193 } 194 return regNum; 195} 196} 197 198Tick 199X86ISA::Interrupts::read(PacketPtr pkt) 200{ 201 Addr offset = pkt->getAddr() - pioAddr; 202 //Make sure we're at least only accessing one register. 203 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 204 panic("Accessed more than one register at a time in the APIC!\n"); 205 ApicRegIndex reg = decodeAddr(offset); 206 uint32_t val = htog(readReg(reg)); 207 DPRINTF(LocalApic, 208 "Reading Local APIC register %d at offset %#x as %#x.\n", 209 reg, offset, val); 210 pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 211 pkt->makeAtomicResponse(); 212 return latency; 213} 214 215Tick 216X86ISA::Interrupts::write(PacketPtr pkt) 217{ 218 Addr offset = pkt->getAddr() - pioAddr; 219 //Make sure we're at least only accessing one register. 220 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 221 panic("Accessed more than one register at a time in the APIC!\n"); 222 ApicRegIndex reg = decodeAddr(offset); 223 uint32_t val = regs[reg]; 224 pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 225 DPRINTF(LocalApic, 226 "Writing Local APIC register %d at offset %#x as %#x.\n", 227 reg, offset, gtoh(val)); 228 setReg(reg, gtoh(val)); 229 pkt->makeAtomicResponse(); 230 return latency; 231} 232void 233X86ISA::Interrupts::requestInterrupt(uint8_t vector, 234 uint8_t deliveryMode, bool level) 235{ 236 /* 237 * Fixed and lowest-priority delivery mode interrupts are handled 238 * using the IRR/ISR registers, checking against the TPR, etc. 239 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 240 */ 241 if (deliveryMode == DeliveryMode::Fixed || 242 deliveryMode == DeliveryMode::LowestPriority) { 243 DPRINTF(LocalApic, "Interrupt is an %s.\n", 244 DeliveryMode::names[deliveryMode]); 245 // Queue up the interrupt in the IRR. 246 if (vector > IRRV) 247 IRRV = vector; 248 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 249 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 250 if (level) { 251 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 252 } else { 253 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 254 } 255 } 256 } else if (!DeliveryMode::isReserved(deliveryMode)) { 257 DPRINTF(LocalApic, "Interrupt is an %s.\n", 258 DeliveryMode::names[deliveryMode]); 259 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 260 pendingUnmaskableInt = pendingSmi = true; 261 smiVector = vector; 262 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 263 pendingUnmaskableInt = pendingNmi = true; 264 nmiVector = vector; 265 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 266 pendingExtInt = true; 267 extIntVector = vector; 268 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 269 pendingUnmaskableInt = pendingInit = true; 270 initVector = vector; 271 } else if (deliveryMode == DeliveryMode::SIPI && 272 !pendingStartup && !startedUp) { 273 pendingUnmaskableInt = pendingStartup = true; 274 startupVector = vector; 275 } 276 } 277 cpu->wakeup(); 278} 279 280 281void 282X86ISA::Interrupts::setCPU(BaseCPU * newCPU) 283{ 284 assert(newCPU); 285 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 286 panic("Local APICs can't be moved between CPUs" 287 " with different IDs.\n"); 288 } 289 cpu = newCPU; 290 initialApicId = cpu->cpuId(); 291 regs[APIC_ID] = (initialApicId << 24); 292} 293 294 295void 296X86ISA::Interrupts::init() 297{ 298 // 299 // The local apic must register its address ranges on both its pio port 300 // via the basicpiodevice(piodevice) init() function and its int port 301 // that it inherited from IntDev. Note IntDev is not a SimObject itself. 302 // 303 BasicPioDevice::init(); 304 IntDev::init(); 305 306 Pc * pc = dynamic_cast<Pc *>(platform); 307 assert(pc); 308 pc->southBridge->ioApic->registerLocalApic(initialApicId, this); 309} 310 311 312Tick 313X86ISA::Interrupts::recvMessage(PacketPtr pkt) 314{ 315 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 316 assert(pkt->cmd == MemCmd::MessageReq); 317 switch(offset) 318 { 319 case 0: 320 { 321 TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 322 DPRINTF(LocalApic, 323 "Got Trigger Interrupt message with vector %#x.\n", 324 message.vector); 325 326 requestInterrupt(message.vector, 327 message.deliveryMode, message.trigger); 328 } 329 break; 330 default: 331 panic("Local apic got unknown interrupt message at offset %#x.\n", 332 offset); 333 break; 334 } 335 pkt->makeAtomicResponse(); 336 return latency; 337} 338 339 340Tick 341X86ISA::Interrupts::recvResponse(PacketPtr pkt) 342{ 343 assert(!pkt->isError()); 344 assert(pkt->cmd == MemCmd::MessageResp); 345 if (--pendingIPIs == 0) { 346 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 347 // Record that the ICR is now idle. 348 low.deliveryStatus = 0; 349 regs[APIC_INTERRUPT_COMMAND_LOW] = low; 350 } 351 DPRINTF(LocalApic, "ICR is now idle.\n"); 352 return 0; 353} 354 355 356void 357X86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 358{ 359 range_list.clear(); 360 Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0), 361 x86LocalAPICAddress(initialApicId, 0) + 362 PageBytes); 363 range_list.push_back(range); 364 pioAddr = range.start; 365} 366 367 368void 369X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 370{ 371 range_list.clear(); 372 range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 373 x86InterruptAddress(initialApicId, 0) + 374 PhysAddrAPICRangeSize)); 375} 376 377 378uint32_t 379X86ISA::Interrupts::readReg(ApicRegIndex reg) 380{ 381 if (reg >= APIC_TRIGGER_MODE(0) && 382 reg <= APIC_TRIGGER_MODE(15)) { 383 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 384 } 385 switch (reg) { 386 case APIC_ARBITRATION_PRIORITY: 387 panic("Local APIC Arbitration Priority register unimplemented.\n"); 388 break; 389 case APIC_PROCESSOR_PRIORITY: 390 panic("Local APIC Processor Priority register unimplemented.\n"); 391 break; 392 case APIC_ERROR_STATUS: 393 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 394 break; 395 case APIC_CURRENT_COUNT: 396 { 397 if (apicTimerEvent.scheduled()) { 398 assert(clock); 399 // Compute how many m5 ticks happen per count. 400 uint64_t ticksPerCount = clock * 401 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 402 // Compute how many m5 ticks are left. 403 uint64_t val = apicTimerEvent.when() - curTick(); 404 // Turn that into a count. 405 val = (val + ticksPerCount - 1) / ticksPerCount; 406 return val; 407 } else { 408 return 0; 409 } 410 } 411 default: 412 break; 413 } 414 return regs[reg]; 415} 416 417void 418X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 419{ 420 uint32_t newVal = val; 421 if (reg >= APIC_IN_SERVICE(0) && 422 reg <= APIC_IN_SERVICE(15)) { 423 panic("Local APIC In-Service registers are unimplemented.\n"); 424 } 425 if (reg >= APIC_TRIGGER_MODE(0) && 426 reg <= APIC_TRIGGER_MODE(15)) { 427 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 428 } 429 if (reg >= APIC_INTERRUPT_REQUEST(0) && 430 reg <= APIC_INTERRUPT_REQUEST(15)) { 431 panic("Local APIC Interrupt Request registers " 432 "are unimplemented.\n"); 433 } 434 switch (reg) { 435 case APIC_ID: 436 newVal = val & 0xFF; 437 break; 438 case APIC_VERSION: 439 // The Local APIC Version register is read only. 440 return; 441 case APIC_TASK_PRIORITY: 442 newVal = val & 0xFF; 443 break; 444 case APIC_ARBITRATION_PRIORITY: 445 panic("Local APIC Arbitration Priority register unimplemented.\n"); 446 break; 447 case APIC_PROCESSOR_PRIORITY: 448 panic("Local APIC Processor Priority register unimplemented.\n"); 449 break; 450 case APIC_EOI: 451 // Remove the interrupt that just completed from the local apic state. 452 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 453 updateISRV(); 454 return; 455 case APIC_LOGICAL_DESTINATION: 456 newVal = val & 0xFF000000; 457 break; 458 case APIC_DESTINATION_FORMAT: 459 newVal = val | 0x0FFFFFFF; 460 break; 461 case APIC_SPURIOUS_INTERRUPT_VECTOR: 462 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 463 regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 464 if (val & (1 << 9)) 465 warn("Focus processor checking not implemented.\n"); 466 break; 467 case APIC_ERROR_STATUS: 468 { 469 if (regs[APIC_INTERNAL_STATE] & 0x1) { 470 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 471 newVal = 0; 472 } else { 473 regs[APIC_INTERNAL_STATE] |= ULL(0x1); 474 return; 475 } 476 477 } 478 break; 479 case APIC_INTERRUPT_COMMAND_LOW: 480 { 481 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 482 // Check if we're already sending an IPI. 483 if (low.deliveryStatus) { 484 newVal = low; 485 break; 486 } 487 low = val; 488 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 489 // Record that an IPI is being sent. 490 low.deliveryStatus = 1; 491 TriggerIntMessage message = 0; 492 message.destination = high.destination; 493 message.vector = low.vector; 494 message.deliveryMode = low.deliveryMode; 495 message.destMode = low.destMode; 496 message.level = low.level; 497 message.trigger = low.trigger; 498 bool timing = sys->getMemoryMode() == Enums::timing; 499 // Be careful no updates of the delivery status bit get lost. 500 regs[APIC_INTERRUPT_COMMAND_LOW] = low; 501 ApicList apics; 502 int numContexts = sys->numContexts(); 503 switch (low.destShorthand) { 504 case 0: 505 if (message.deliveryMode == DeliveryMode::LowestPriority) { 506 panic("Lowest priority delivery mode " 507 "IPIs aren't implemented.\n"); 508 } 509 if (message.destMode == 1) { 510 int dest = message.destination; 511 hack_once("Assuming logical destinations are 1 << id.\n"); 512 for (int i = 0; i < numContexts; i++) { 513 if (dest & 0x1) 514 apics.push_back(i); 515 dest = dest >> 1; 516 } 517 } else { 518 if (message.destination == 0xFF) { 519 for (int i = 0; i < numContexts; i++) { 520 if (i == initialApicId) { 521 requestInterrupt(message.vector, 522 message.deliveryMode, message.trigger); 523 } else { 524 apics.push_back(i); 525 } 526 } 527 } else { 528 if (message.destination == initialApicId) { 529 requestInterrupt(message.vector, 530 message.deliveryMode, message.trigger); 531 } else { 532 apics.push_back(message.destination); 533 } 534 } 535 } 536 break; 537 case 1: 538 newVal = val; 539 requestInterrupt(message.vector, 540 message.deliveryMode, message.trigger); 541 break; 542 case 2: 543 requestInterrupt(message.vector, 544 message.deliveryMode, message.trigger); 545 // Fall through 546 case 3: 547 { 548 for (int i = 0; i < numContexts; i++) { 549 if (i != initialApicId) { 550 apics.push_back(i); 551 } 552 } 553 } 554 break; 555 } 556 pendingIPIs += apics.size(); 557 intPort->sendMessage(apics, message, timing); 558 newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 559 } 560 break; 561 case APIC_LVT_TIMER: 562 case APIC_LVT_THERMAL_SENSOR: 563 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 564 case APIC_LVT_LINT0: 565 case APIC_LVT_LINT1: 566 case APIC_LVT_ERROR: 567 { 568 uint64_t readOnlyMask = (1 << 12) | (1 << 14); 569 newVal = (val & ~readOnlyMask) | 570 (regs[reg] & readOnlyMask); 571 } 572 break; 573 case APIC_INITIAL_COUNT: 574 { 575 assert(clock); 576 newVal = bits(val, 31, 0); 577 // Compute how many timer ticks we're being programmed for. 578 uint64_t newCount = newVal * 579 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 580 // Schedule on the edge of the next tick plus the new count. 581 Tick offset = curTick() % clock; 582 if (offset) { 583 reschedule(apicTimerEvent, 584 curTick() + (newCount + 1) * clock - offset, true); 585 } else { 586 reschedule(apicTimerEvent, 587 curTick() + newCount * clock, true); 588 } 589 } 590 break; 591 case APIC_CURRENT_COUNT: 592 //Local APIC Current Count register is read only. 593 return; 594 case APIC_DIVIDE_CONFIGURATION: 595 newVal = val & 0xB; 596 break; 597 default: 598 break; 599 } 600 regs[reg] = newVal; 601 return; 602} 603 604 605X86ISA::Interrupts::Interrupts(Params * p) : 606 BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency), 607 clock(0), 608 apicTimerEvent(this), 609 pendingSmi(false), smiVector(0), 610 pendingNmi(false), nmiVector(0), 611 pendingExtInt(false), extIntVector(0), 612 pendingInit(false), initVector(0), 613 pendingStartup(false), startupVector(0), 614 startedUp(false), pendingUnmaskableInt(false), 615 pendingIPIs(0), cpu(NULL) 616{ 617 pioSize = PageBytes; 618 memset(regs, 0, sizeof(regs)); 619 //Set the local apic DFR to the flat model. 620 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 621 ISRV = 0; 622 IRRV = 0; 623} 624 625 626bool 627X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 628{ 629 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 630 if (pendingUnmaskableInt) { 631 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 632 return true; 633 } 634 if (rflags.intf) { 635 if (pendingExtInt) { 636 DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 637 return true; 638 } 639 if (IRRV > ISRV && bits(IRRV, 7, 4) > 640 bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 641 DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 642 return true; 643 } 644 } 645 return false; 646} 647 648Fault 649X86ISA::Interrupts::getInterrupt(ThreadContext *tc) 650{ 651 assert(checkInterrupts(tc)); 652 // These are all probably fairly uncommon, so we'll make them easier to 653 // check for. 654 if (pendingUnmaskableInt) { 655 if (pendingSmi) { 656 DPRINTF(LocalApic, "Generated SMI fault object.\n"); 657 return new SystemManagementInterrupt(); 658 } else if (pendingNmi) { 659 DPRINTF(LocalApic, "Generated NMI fault object.\n"); 660 return new NonMaskableInterrupt(nmiVector); 661 } else if (pendingInit) { 662 DPRINTF(LocalApic, "Generated INIT fault object.\n"); 663 return new InitInterrupt(initVector); 664 } else if (pendingStartup) { 665 DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 666 return new StartupInterrupt(startupVector); 667 } else { 668 panic("pendingUnmaskableInt set, but no unmaskable " 669 "ints were pending.\n"); 670 return NoFault; 671 } 672 } else if (pendingExtInt) { 673 DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 674 return new ExternalInterrupt(extIntVector); 675 } else { 676 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 677 // The only thing left are fixed and lowest priority interrupts. 678 return new ExternalInterrupt(IRRV); 679 } 680} 681 682void 683X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 684{ 685 assert(checkInterrupts(tc)); 686 if (pendingUnmaskableInt) { 687 if (pendingSmi) { 688 DPRINTF(LocalApic, "SMI sent to core.\n"); 689 pendingSmi = false; 690 } else if (pendingNmi) { 691 DPRINTF(LocalApic, "NMI sent to core.\n"); 692 pendingNmi = false; 693 } else if (pendingInit) { 694 DPRINTF(LocalApic, "Init sent to core.\n"); 695 pendingInit = false; 696 startedUp = false; 697 } else if (pendingStartup) { 698 DPRINTF(LocalApic, "SIPI sent to core.\n"); 699 pendingStartup = false; 700 startedUp = true; 701 } 702 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 703 pendingUnmaskableInt = false; 704 } else if (pendingExtInt) { 705 pendingExtInt = false; 706 } else { 707 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 708 // Mark the interrupt as "in service". 709 ISRV = IRRV; 710 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 711 // Clear it out of the IRR. 712 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 713 updateIRRV(); 714 } 715} 716 717void 718X86ISA::Interrupts::serialize(std::ostream &os) 719{ 720 SERIALIZE_ARRAY(regs, NUM_APIC_REGS); 721 SERIALIZE_SCALAR(clock); 722 SERIALIZE_SCALAR(pendingSmi); 723 SERIALIZE_SCALAR(smiVector); 724 SERIALIZE_SCALAR(pendingNmi); 725 SERIALIZE_SCALAR(nmiVector); 726 SERIALIZE_SCALAR(pendingExtInt); 727 SERIALIZE_SCALAR(extIntVector); 728 SERIALIZE_SCALAR(pendingInit); 729 SERIALIZE_SCALAR(initVector); 730 SERIALIZE_SCALAR(pendingStartup); 731 SERIALIZE_SCALAR(startupVector); 732 SERIALIZE_SCALAR(startedUp); 733 SERIALIZE_SCALAR(pendingUnmaskableInt); 734 SERIALIZE_SCALAR(pendingIPIs); 735 SERIALIZE_SCALAR(IRRV); 736 SERIALIZE_SCALAR(ISRV); 737 bool apicTimerEventScheduled = apicTimerEvent.scheduled(); 738 SERIALIZE_SCALAR(apicTimerEventScheduled); 739 Tick apicTimerEventTick = apicTimerEvent.when(); 740 SERIALIZE_SCALAR(apicTimerEventTick); 741} 742 743void 744X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion) 745{ 746 UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS); 747 UNSERIALIZE_SCALAR(clock); 748 UNSERIALIZE_SCALAR(pendingSmi); 749 UNSERIALIZE_SCALAR(smiVector); 750 UNSERIALIZE_SCALAR(pendingNmi); 751 UNSERIALIZE_SCALAR(nmiVector); 752 UNSERIALIZE_SCALAR(pendingExtInt); 753 UNSERIALIZE_SCALAR(extIntVector); 754 UNSERIALIZE_SCALAR(pendingInit); 755 UNSERIALIZE_SCALAR(initVector); 756 UNSERIALIZE_SCALAR(pendingStartup); 757 UNSERIALIZE_SCALAR(startupVector); 758 UNSERIALIZE_SCALAR(startedUp); 759 UNSERIALIZE_SCALAR(pendingUnmaskableInt); 760 UNSERIALIZE_SCALAR(pendingIPIs); 761 UNSERIALIZE_SCALAR(IRRV); 762 UNSERIALIZE_SCALAR(ISRV); 763 bool apicTimerEventScheduled; 764 UNSERIALIZE_SCALAR(apicTimerEventScheduled); 765 if (apicTimerEventScheduled) { 766 Tick apicTimerEventTick; 767 UNSERIALIZE_SCALAR(apicTimerEventTick); 768 if (apicTimerEvent.scheduled()) { 769 reschedule(apicTimerEvent, apicTimerEventTick, true); 770 } else { 771 schedule(apicTimerEvent, apicTimerEventTick); 772 } 773 } 774} 775 776X86ISA::Interrupts * 777X86LocalApicParams::create() 778{ 779 return new X86ISA::Interrupts(this); 780} 781