interrupts.cc revision 6712
15647Sgblack@eecs.umich.edu/* 29544Sandreas.hansson@arm.com * Copyright (c) 2008 The Hewlett-Packard Development Company 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * Redistribution and use of this software in source and binary forms, 68922Swilliam.wang@arm.com * with or without modification, are permitted provided that the 78922Swilliam.wang@arm.com * following conditions are met: 88922Swilliam.wang@arm.com * 98922Swilliam.wang@arm.com * The software must be used only for Non-Commercial Use which means any 108922Swilliam.wang@arm.com * use which is NOT directed to receiving any direct monetary 118922Swilliam.wang@arm.com * compensation for, or commercial advantage from such use. Illustrative 128922Swilliam.wang@arm.com * examples of non-commercial use are academic research, personal study, 138922Swilliam.wang@arm.com * teaching, education and corporate research & development. 145647Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 155647Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 165647Sgblack@eecs.umich.edu * commercial advantage. 177087Snate@binkert.org * 187087Snate@binkert.org * If you wish to use this software or functionality therein that may be 197087Snate@binkert.org * covered by patents for commercial use, please contact: 207087Snate@binkert.org * Director of Intellectual Property Licensing 217087Snate@binkert.org * Office of Strategy and Technology 227087Snate@binkert.org * Hewlett-Packard Company 237087Snate@binkert.org * 1501 Page Mill Road 247087Snate@binkert.org * Palo Alto, California 94304 255647Sgblack@eecs.umich.edu * 267087Snate@binkert.org * Redistributions of source code must retain the above copyright notice, 277087Snate@binkert.org * this list of conditions and the following disclaimer. Redistributions 287087Snate@binkert.org * in binary form must reproduce the above copyright notice, this list of 297087Snate@binkert.org * conditions and the following disclaimer in the documentation and/or 307087Snate@binkert.org * other materials provided with the distribution. Neither the name of 317087Snate@binkert.org * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 327087Snate@binkert.org * contributors may be used to endorse or promote products derived from 337087Snate@binkert.org * this software without specific prior written permission. No right of 345647Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 357087Snate@binkert.org * output created using the software may be prepared, but only for 365647Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 375647Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 385647Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 395647Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 405647Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 415647Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 425647Sgblack@eecs.umich.edu * 435647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 445647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 455647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 465647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 475647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 528229Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545654Sgblack@eecs.umich.edu * 555647Sgblack@eecs.umich.edu * Authors: Gabe Black 568232Snate@binkert.org */ 576137Sgblack@eecs.umich.edu 586137Sgblack@eecs.umich.edu#include "arch/x86/apicregs.hh" 596137Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 605654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 616046Sgblack@eecs.umich.edu#include "cpu/base.hh" 628781Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 635647Sgblack@eecs.umich.edu#include "dev/x86/pc.hh" 645648Sgblack@eecs.umich.edu#include "dev/x86/south_bridge.hh" 655648Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 665647Sgblack@eecs.umich.edu#include "sim/system.hh" 675647Sgblack@eecs.umich.edu 685647Sgblack@eecs.umich.eduint 695647Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 705647Sgblack@eecs.umich.edu{ 715647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 725647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 735647Sgblack@eecs.umich.edu // be deciphered fairly easily. 745647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 755648Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 765647Sgblack@eecs.umich.edu return 1 << shift; 775648Sgblack@eecs.umich.edu} 785648Sgblack@eecs.umich.edu 795648Sgblack@eecs.umich.edunamespace X86ISA 805648Sgblack@eecs.umich.edu{ 815648Sgblack@eecs.umich.edu 825648Sgblack@eecs.umich.eduApicRegIndex 835648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 845648Sgblack@eecs.umich.edu{ 855648Sgblack@eecs.umich.edu ApicRegIndex regNum; 865648Sgblack@eecs.umich.edu paddr &= ~mask(3); 875648Sgblack@eecs.umich.edu switch (paddr) 885648Sgblack@eecs.umich.edu { 895648Sgblack@eecs.umich.edu case 0x20: 905648Sgblack@eecs.umich.edu regNum = APIC_ID; 915648Sgblack@eecs.umich.edu break; 925648Sgblack@eecs.umich.edu case 0x30: 935648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 945648Sgblack@eecs.umich.edu break; 955648Sgblack@eecs.umich.edu case 0x80: 965648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 975648Sgblack@eecs.umich.edu break; 985648Sgblack@eecs.umich.edu case 0x90: 995648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 1005648Sgblack@eecs.umich.edu break; 1015648Sgblack@eecs.umich.edu case 0xA0: 1025648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 1035648Sgblack@eecs.umich.edu break; 1045648Sgblack@eecs.umich.edu case 0xB0: 1055648Sgblack@eecs.umich.edu regNum = APIC_EOI; 1065648Sgblack@eecs.umich.edu break; 1075648Sgblack@eecs.umich.edu case 0xD0: 1085648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 1095648Sgblack@eecs.umich.edu break; 1105648Sgblack@eecs.umich.edu case 0xE0: 1115648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 1125648Sgblack@eecs.umich.edu break; 1135648Sgblack@eecs.umich.edu case 0xF0: 1145648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 1155648Sgblack@eecs.umich.edu break; 1165648Sgblack@eecs.umich.edu case 0x100: 1175648Sgblack@eecs.umich.edu case 0x108: 1185648Sgblack@eecs.umich.edu case 0x110: 1195648Sgblack@eecs.umich.edu case 0x118: 1205648Sgblack@eecs.umich.edu case 0x120: 1215648Sgblack@eecs.umich.edu case 0x128: 1225648Sgblack@eecs.umich.edu case 0x130: 1235648Sgblack@eecs.umich.edu case 0x138: 1245648Sgblack@eecs.umich.edu case 0x140: 1255648Sgblack@eecs.umich.edu case 0x148: 1265648Sgblack@eecs.umich.edu case 0x150: 1275648Sgblack@eecs.umich.edu case 0x158: 1285648Sgblack@eecs.umich.edu case 0x160: 1295648Sgblack@eecs.umich.edu case 0x168: 1305648Sgblack@eecs.umich.edu case 0x170: 1315648Sgblack@eecs.umich.edu case 0x178: 1325648Sgblack@eecs.umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1335648Sgblack@eecs.umich.edu break; 1345648Sgblack@eecs.umich.edu case 0x180: 1355648Sgblack@eecs.umich.edu case 0x188: 1365648Sgblack@eecs.umich.edu case 0x190: 1375648Sgblack@eecs.umich.edu case 0x198: 1385648Sgblack@eecs.umich.edu case 0x1A0: 1395648Sgblack@eecs.umich.edu case 0x1A8: 1405648Sgblack@eecs.umich.edu case 0x1B0: 1415648Sgblack@eecs.umich.edu case 0x1B8: 1425648Sgblack@eecs.umich.edu case 0x1C0: 1435648Sgblack@eecs.umich.edu case 0x1C8: 1445648Sgblack@eecs.umich.edu case 0x1D0: 1455648Sgblack@eecs.umich.edu case 0x1D8: 1465648Sgblack@eecs.umich.edu case 0x1E0: 1475648Sgblack@eecs.umich.edu case 0x1E8: 1485648Sgblack@eecs.umich.edu case 0x1F0: 1495648Sgblack@eecs.umich.edu case 0x1F8: 1505648Sgblack@eecs.umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1515648Sgblack@eecs.umich.edu break; 1525648Sgblack@eecs.umich.edu case 0x200: 1535648Sgblack@eecs.umich.edu case 0x208: 1545648Sgblack@eecs.umich.edu case 0x210: 1555648Sgblack@eecs.umich.edu case 0x218: 1565648Sgblack@eecs.umich.edu case 0x220: 1575648Sgblack@eecs.umich.edu case 0x228: 1585648Sgblack@eecs.umich.edu case 0x230: 1595648Sgblack@eecs.umich.edu case 0x238: 1605648Sgblack@eecs.umich.edu case 0x240: 1615648Sgblack@eecs.umich.edu case 0x248: 1625648Sgblack@eecs.umich.edu case 0x250: 1635648Sgblack@eecs.umich.edu case 0x258: 1645648Sgblack@eecs.umich.edu case 0x260: 1655648Sgblack@eecs.umich.edu case 0x268: 1665648Sgblack@eecs.umich.edu case 0x270: 1675648Sgblack@eecs.umich.edu case 0x278: 1685648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1695648Sgblack@eecs.umich.edu break; 1705648Sgblack@eecs.umich.edu case 0x280: 1715648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1725648Sgblack@eecs.umich.edu break; 1735648Sgblack@eecs.umich.edu case 0x300: 1745648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1755648Sgblack@eecs.umich.edu break; 1765648Sgblack@eecs.umich.edu case 0x310: 1775648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1785648Sgblack@eecs.umich.edu break; 1795648Sgblack@eecs.umich.edu case 0x320: 1805648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1815648Sgblack@eecs.umich.edu break; 1825648Sgblack@eecs.umich.edu case 0x330: 1835648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1845648Sgblack@eecs.umich.edu break; 1855648Sgblack@eecs.umich.edu case 0x340: 1865648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1875648Sgblack@eecs.umich.edu break; 1885648Sgblack@eecs.umich.edu case 0x350: 1895648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1905648Sgblack@eecs.umich.edu break; 1915648Sgblack@eecs.umich.edu case 0x360: 1925648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1935648Sgblack@eecs.umich.edu break; 1945648Sgblack@eecs.umich.edu case 0x370: 1955648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1965648Sgblack@eecs.umich.edu break; 1975648Sgblack@eecs.umich.edu case 0x380: 1985648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1995648Sgblack@eecs.umich.edu break; 2005648Sgblack@eecs.umich.edu case 0x390: 2015648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 2025648Sgblack@eecs.umich.edu break; 2035648Sgblack@eecs.umich.edu case 0x3E0: 2045648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 2055648Sgblack@eecs.umich.edu break; 2065648Sgblack@eecs.umich.edu default: 2075648Sgblack@eecs.umich.edu // A reserved register field. 2085648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 2095648Sgblack@eecs.umich.edu break; 2105648Sgblack@eecs.umich.edu } 2115648Sgblack@eecs.umich.edu return regNum; 2125648Sgblack@eecs.umich.edu} 2135648Sgblack@eecs.umich.edu} 2145648Sgblack@eecs.umich.edu 2155648Sgblack@eecs.umich.eduTick 2165648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 2175648Sgblack@eecs.umich.edu{ 2185648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2195648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2205649Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2215649Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2225649Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2235648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 2245898Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2259805Sstever@gmail.com "Reading Local APIC register %d at offset %#x as %#x.\n", 2265648Sgblack@eecs.umich.edu reg, offset, val); 2275648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2285648Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2295648Sgblack@eecs.umich.edu return latency; 2305648Sgblack@eecs.umich.edu} 2315648Sgblack@eecs.umich.edu 2325648Sgblack@eecs.umich.eduTick 2335648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2345648Sgblack@eecs.umich.edu{ 2355648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2365648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2375648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2385649Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2395649Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2405649Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2415648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2425898Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2439805Sstever@gmail.com "Writing Local APIC register %d at offset %#x as %#x.\n", 2445647Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2455691Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2465691Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2475691Sgblack@eecs.umich.edu return latency; 2485691Sgblack@eecs.umich.edu} 2495691Sgblack@eecs.umich.eduvoid 2505691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2515691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2525691Sgblack@eecs.umich.edu{ 2535691Sgblack@eecs.umich.edu /* 2545691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2555691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2565691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2575691Sgblack@eecs.umich.edu */ 2585691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2595691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2605691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2615691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2625691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2635691Sgblack@eecs.umich.edu if (vector > IRRV) 2645691Sgblack@eecs.umich.edu IRRV = vector; 2655691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2665691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2675691Sgblack@eecs.umich.edu if (level) { 2685691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2695691Sgblack@eecs.umich.edu } else { 2705691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2715691Sgblack@eecs.umich.edu } 2725691Sgblack@eecs.umich.edu } 2735691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2745691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2755691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2765691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2775691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2785691Sgblack@eecs.umich.edu smiVector = vector; 2795691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2805691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2815691Sgblack@eecs.umich.edu nmiVector = vector; 2825691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2835691Sgblack@eecs.umich.edu pendingExtInt = true; 2846066Sgblack@eecs.umich.edu extIntVector = vector; 2856066Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2866050Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2876050Sgblack@eecs.umich.edu initVector = vector; 2885691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && 2898745Sgblack@eecs.umich.edu !pendingStartup && !startedUp) { 2908781Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2918781Sgblack@eecs.umich.edu startupVector = vector; 2925691Sgblack@eecs.umich.edu } 2935647Sgblack@eecs.umich.edu } 2946041Sgblack@eecs.umich.edu cpu->wakeup(); 2956041Sgblack@eecs.umich.edu} 2966041Sgblack@eecs.umich.edu 2976041Sgblack@eecs.umich.edu 2986136Sgblack@eecs.umich.eduvoid 2996136Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 3006136Sgblack@eecs.umich.edu{ 3016136Sgblack@eecs.umich.edu assert(newCPU); 3026136Sgblack@eecs.umich.edu if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 3036041Sgblack@eecs.umich.edu panic("Local APICs can't be moved between CPUs" 3046136Sgblack@eecs.umich.edu " with different IDs.\n"); 3056136Sgblack@eecs.umich.edu } 3069090Sandreas.hansson@arm.com cpu = newCPU; 3076041Sgblack@eecs.umich.edu initialApicId = cpu->cpuId(); 3086041Sgblack@eecs.umich.edu regs[APIC_ID] = (initialApicId << 24); 3096041Sgblack@eecs.umich.edu} 3106137Sgblack@eecs.umich.edu 3116137Sgblack@eecs.umich.edu 3126137Sgblack@eecs.umich.eduvoid 3137913SBrad.Beckmann@amd.comX86ISA::Interrupts::init() 3149807Sstever@gmail.com{ 3159807Sstever@gmail.com BasicPioDevice::init(); 3169807Sstever@gmail.com Pc * pc = dynamic_cast<Pc *>(platform); 3179807Sstever@gmail.com assert(pc); 3187913SBrad.Beckmann@amd.com pc->southBridge->ioApic->registerLocalApic(initialApicId, this); 3196137Sgblack@eecs.umich.edu} 3209807Sstever@gmail.com 3218922Swilliam.wang@arm.com 3228922Swilliam.wang@arm.comTick 3238922Swilliam.wang@arm.comX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3246137Sgblack@eecs.umich.edu{ 3256137Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 3266137Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3275651Sgblack@eecs.umich.edu switch(offset) 3285651Sgblack@eecs.umich.edu { 3295651Sgblack@eecs.umich.edu case 0: 3306136Sgblack@eecs.umich.edu { 3315651Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3325651Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3335651Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3345651Sgblack@eecs.umich.edu message.vector); 3355654Sgblack@eecs.umich.edu 3365654Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3375654Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3385654Sgblack@eecs.umich.edu } 3395697Snate@binkert.org break; 3405655Sgblack@eecs.umich.edu default: 3415691Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3425691Sgblack@eecs.umich.edu offset); 3435654Sgblack@eecs.umich.edu break; 3445651Sgblack@eecs.umich.edu } 3455651Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 3465651Sgblack@eecs.umich.edu return latency; 3475651Sgblack@eecs.umich.edu} 3485651Sgblack@eecs.umich.edu 3495651Sgblack@eecs.umich.edu 3506064Sgblack@eecs.umich.eduTick 3519805Sstever@gmail.comX86ISA::Interrupts::recvResponse(PacketPtr pkt) 3525651Sgblack@eecs.umich.edu{ 3535651Sgblack@eecs.umich.edu assert(!pkt->isError()); 3545651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageResp); 3556065Sgblack@eecs.umich.edu if (--pendingIPIs == 0) { 3566065Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 3576065Sgblack@eecs.umich.edu // Record that the ICR is now idle. 3586065Sgblack@eecs.umich.edu low.deliveryStatus = 0; 3596065Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 3606069Sgblack@eecs.umich.edu } 3616069Sgblack@eecs.umich.edu delete pkt->req; 3626069Sgblack@eecs.umich.edu delete pkt; 3636069Sgblack@eecs.umich.edu DPRINTF(LocalApic, "ICR is now idle.\n"); 3646069Sgblack@eecs.umich.edu return 0; 3656069Sgblack@eecs.umich.edu} 3666065Sgblack@eecs.umich.edu 3676065Sgblack@eecs.umich.edu 3686065Sgblack@eecs.umich.eduvoid 3696065Sgblack@eecs.umich.eduX86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 3706065Sgblack@eecs.umich.edu{ 3718711Sandreas.hansson@arm.com range_list.clear(); 3729090Sandreas.hansson@arm.com Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0), 3736041Sgblack@eecs.umich.edu x86LocalAPICAddress(initialApicId, 0) + 3748711Sandreas.hansson@arm.com PageBytes); 3758711Sandreas.hansson@arm.com range_list.push_back(range); 3768711Sandreas.hansson@arm.com pioAddr = range.start; 3778711Sandreas.hansson@arm.com} 3788711Sandreas.hansson@arm.com 3796041Sgblack@eecs.umich.edu 3806041Sgblack@eecs.umich.eduvoid 3816041Sgblack@eecs.umich.eduX86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 3825647Sgblack@eecs.umich.edu{ 3835648Sgblack@eecs.umich.edu range_list.clear(); 3845647Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 3855647Sgblack@eecs.umich.edu x86InterruptAddress(initialApicId, 0) + 3865647Sgblack@eecs.umich.edu PhysAddrAPICRangeSize)); 3875647Sgblack@eecs.umich.edu} 3885647Sgblack@eecs.umich.edu 3895647Sgblack@eecs.umich.edu 3905647Sgblack@eecs.umich.eduuint32_t 3915647Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3925647Sgblack@eecs.umich.edu{ 3935647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3945647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3955647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3965647Sgblack@eecs.umich.edu } 3975647Sgblack@eecs.umich.edu switch (reg) { 3985647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3995647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4005647Sgblack@eecs.umich.edu break; 4015848Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4025848Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4039544Sandreas.hansson@arm.com break; 4045848Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4055848Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4067823Ssteve.reinhardt@amd.com break; 4075848Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 4085848Sgblack@eecs.umich.edu { 4095848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 4105848Sgblack@eecs.umich.edu assert(clock); 4115848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 4125848Sgblack@eecs.umich.edu uint64_t ticksPerCount = clock * 4135647Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 4145647Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 4155647Sgblack@eecs.umich.edu uint64_t val = apicTimerEvent.when() - curTick; 4165647Sgblack@eecs.umich.edu // Turn that into a count. 4175648Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 4185647Sgblack@eecs.umich.edu return val; 4195647Sgblack@eecs.umich.edu } else { 4205647Sgblack@eecs.umich.edu return 0; 4215648Sgblack@eecs.umich.edu } 4225647Sgblack@eecs.umich.edu } 4235647Sgblack@eecs.umich.edu default: 4245647Sgblack@eecs.umich.edu break; 4255647Sgblack@eecs.umich.edu } 4265647Sgblack@eecs.umich.edu return regs[reg]; 4275647Sgblack@eecs.umich.edu} 4285647Sgblack@eecs.umich.edu 4295647Sgblack@eecs.umich.eduvoid 4305647Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 4315647Sgblack@eecs.umich.edu{ 4325647Sgblack@eecs.umich.edu uint32_t newVal = val; 4335647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4345647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4355647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4365647Sgblack@eecs.umich.edu } 4375647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4385647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4395647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4405647Sgblack@eecs.umich.edu } 4415647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4425647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4435647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4445647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4455647Sgblack@eecs.umich.edu } 4465647Sgblack@eecs.umich.edu switch (reg) { 4475647Sgblack@eecs.umich.edu case APIC_ID: 4485647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4495647Sgblack@eecs.umich.edu break; 4505647Sgblack@eecs.umich.edu case APIC_VERSION: 4515647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4525647Sgblack@eecs.umich.edu return; 4535647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4545690Sgblack@eecs.umich.edu newVal = val & 0xFF; 4555690Sgblack@eecs.umich.edu break; 4565690Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4575690Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4585647Sgblack@eecs.umich.edu break; 4595647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4605647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4615647Sgblack@eecs.umich.edu break; 4625647Sgblack@eecs.umich.edu case APIC_EOI: 4635647Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4645647Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4655647Sgblack@eecs.umich.edu updateISRV(); 4665647Sgblack@eecs.umich.edu return; 4675647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4685647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4695647Sgblack@eecs.umich.edu break; 4705647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4715647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4725647Sgblack@eecs.umich.edu break; 4735647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4745647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4755647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4765647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4775647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4785647Sgblack@eecs.umich.edu break; 4795647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4805647Sgblack@eecs.umich.edu { 4815647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4825647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4836046Sgblack@eecs.umich.edu newVal = 0; 4846046Sgblack@eecs.umich.edu } else { 4856046Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4866046Sgblack@eecs.umich.edu return; 4876046Sgblack@eecs.umich.edu } 4886046Sgblack@eecs.umich.edu 4896046Sgblack@eecs.umich.edu } 4906046Sgblack@eecs.umich.edu break; 4916046Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4926046Sgblack@eecs.umich.edu { 4936046Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 4946712Snate@binkert.org // Check if we're already sending an IPI. 4956046Sgblack@eecs.umich.edu if (low.deliveryStatus) { 4966046Sgblack@eecs.umich.edu newVal = low; 4976046Sgblack@eecs.umich.edu break; 4986046Sgblack@eecs.umich.edu } 4996046Sgblack@eecs.umich.edu low = val; 5006046Sgblack@eecs.umich.edu InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 5019524SAndreas.Sandberg@ARM.com // Record that an IPI is being sent. 5026065Sgblack@eecs.umich.edu low.deliveryStatus = 1; 5036065Sgblack@eecs.umich.edu TriggerIntMessage message = 0; 5046138Sgblack@eecs.umich.edu message.destination = high.destination; 5056138Sgblack@eecs.umich.edu message.vector = low.vector; 5066046Sgblack@eecs.umich.edu message.deliveryMode = low.deliveryMode; 5076046Sgblack@eecs.umich.edu message.destMode = low.destMode; 5086138Sgblack@eecs.umich.edu message.level = low.level; 5096138Sgblack@eecs.umich.edu message.trigger = low.trigger; 5106138Sgblack@eecs.umich.edu bool timing = sys->getMemoryMode() == Enums::timing; 5116138Sgblack@eecs.umich.edu // Be careful no updates of the delivery status bit get lost. 5126138Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 5136138Sgblack@eecs.umich.edu ApicList apics; 5146138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 5156138Sgblack@eecs.umich.edu switch (low.destShorthand) { 5166138Sgblack@eecs.umich.edu case 0: 5176138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 5186138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode " 5196138Sgblack@eecs.umich.edu "IPIs aren't implemented.\n"); 5206138Sgblack@eecs.umich.edu } 5216138Sgblack@eecs.umich.edu if (message.destMode == 1) { 5226138Sgblack@eecs.umich.edu int dest = message.destination; 5236138Sgblack@eecs.umich.edu hack_once("Assuming logical destinations are 1 << id.\n"); 5246138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5256138Sgblack@eecs.umich.edu if (dest & 0x1) 5266138Sgblack@eecs.umich.edu apics.push_back(i); 5276138Sgblack@eecs.umich.edu dest = dest >> 1; 5286138Sgblack@eecs.umich.edu } 5296138Sgblack@eecs.umich.edu } else { 5306138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 5316138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5326138Sgblack@eecs.umich.edu if (i == initialApicId) { 5336138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5346138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5356138Sgblack@eecs.umich.edu } else { 5366138Sgblack@eecs.umich.edu apics.push_back(i); 5376138Sgblack@eecs.umich.edu } 5386138Sgblack@eecs.umich.edu } 5396046Sgblack@eecs.umich.edu } else { 5406046Sgblack@eecs.umich.edu if (message.destination == initialApicId) { 5416069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5426069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5436069Sgblack@eecs.umich.edu } else { 5446046Sgblack@eecs.umich.edu apics.push_back(message.destination); 5456046Sgblack@eecs.umich.edu } 5466069Sgblack@eecs.umich.edu } 5476069Sgblack@eecs.umich.edu } 5486069Sgblack@eecs.umich.edu break; 5496046Sgblack@eecs.umich.edu case 1: 5506069Sgblack@eecs.umich.edu newVal = val; 5516069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5526138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5536138Sgblack@eecs.umich.edu break; 5546069Sgblack@eecs.umich.edu case 2: 5556069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5566069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5576046Sgblack@eecs.umich.edu // Fall through 5586046Sgblack@eecs.umich.edu case 3: 5596138Sgblack@eecs.umich.edu { 5608922Swilliam.wang@arm.com for (int i = 0; i < numContexts; i++) { 5616138Sgblack@eecs.umich.edu if (i != initialApicId) { 5626046Sgblack@eecs.umich.edu apics.push_back(i); 5635647Sgblack@eecs.umich.edu } 5645647Sgblack@eecs.umich.edu } 5655647Sgblack@eecs.umich.edu } 5665647Sgblack@eecs.umich.edu break; 5675647Sgblack@eecs.umich.edu } 5685647Sgblack@eecs.umich.edu pendingIPIs += apics.size(); 5695647Sgblack@eecs.umich.edu intPort->sendMessage(apics, message, timing); 5705647Sgblack@eecs.umich.edu newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 5715647Sgblack@eecs.umich.edu } 5725647Sgblack@eecs.umich.edu break; 5735647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 5745647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 5755647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 5765647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 5775648Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 5785648Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 5795848Sgblack@eecs.umich.edu { 5805848Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 5815848Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 5825648Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 5839544Sandreas.hansson@arm.com } 5845648Sgblack@eecs.umich.edu break; 5855648Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 5869544Sandreas.hansson@arm.com { 5879544Sandreas.hansson@arm.com assert(clock); 5885648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 5899623Snilay@cs.wisc.edu // Compute how many timer ticks we're being programmed for. 5909623Snilay@cs.wisc.edu uint64_t newCount = newVal * 5919623Snilay@cs.wisc.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 5929623Snilay@cs.wisc.edu // Schedule on the edge of the next tick plus the new count. 5935648Sgblack@eecs.umich.edu Tick offset = curTick % clock; 5945648Sgblack@eecs.umich.edu if (offset) { 5955647Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5965647Sgblack@eecs.umich.edu curTick + (newCount + 1) * clock - offset, true); 5975647Sgblack@eecs.umich.edu } else { 5985647Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5995647Sgblack@eecs.umich.edu curTick + newCount * clock, true); 6005647Sgblack@eecs.umich.edu } 6015647Sgblack@eecs.umich.edu } 6025647Sgblack@eecs.umich.edu break; 6035647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 6045647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 6055648Sgblack@eecs.umich.edu return; 6065647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 6075647Sgblack@eecs.umich.edu newVal = val & 0xB; 6085647Sgblack@eecs.umich.edu break; 6096041Sgblack@eecs.umich.edu default: 6109807Sstever@gmail.com break; 6119808Sstever@gmail.com } 6129807Sstever@gmail.com regs[reg] = newVal; 6139807Sstever@gmail.com return; 6149807Sstever@gmail.com} 6159807Sstever@gmail.com 6169807Sstever@gmail.com 6179807Sstever@gmail.comX86ISA::Interrupts::Interrupts(Params * p) : 6189807Sstever@gmail.com BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0), 6199807Sstever@gmail.com apicTimerEvent(this), 6209807Sstever@gmail.com pendingSmi(false), smiVector(0), 6216041Sgblack@eecs.umich.edu pendingNmi(false), nmiVector(0), 6226041Sgblack@eecs.umich.edu pendingExtInt(false), extIntVector(0), 6236041Sgblack@eecs.umich.edu pendingInit(false), initVector(0), 6246041Sgblack@eecs.umich.edu pendingStartup(false), startupVector(0), 6256041Sgblack@eecs.umich.edu startedUp(false), pendingUnmaskableInt(false), 6266041Sgblack@eecs.umich.edu pendingIPIs(0), cpu(NULL) 6276041Sgblack@eecs.umich.edu{ 6286041Sgblack@eecs.umich.edu pioSize = PageBytes; 6296041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 6305654Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 6315704Snate@binkert.org regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 6325654Sgblack@eecs.umich.edu ISRV = 0; 6335654Sgblack@eecs.umich.edu IRRV = 0; 6345689Sgblack@eecs.umich.edu} 6355689Sgblack@eecs.umich.edu 6365654Sgblack@eecs.umich.edu 6375689Sgblack@eecs.umich.edubool 6385655Sgblack@eecs.umich.eduX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 6395689Sgblack@eecs.umich.edu{ 6405689Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 6415655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6425689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 6435655Sgblack@eecs.umich.edu return true; 6445689Sgblack@eecs.umich.edu } 6455689Sgblack@eecs.umich.edu if (rflags.intf) { 6465655Sgblack@eecs.umich.edu if (pendingExtInt) { 6475689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 6485654Sgblack@eecs.umich.edu return true; 6495654Sgblack@eecs.umich.edu } 6505654Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 6515654Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 6525654Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 6535704Snate@binkert.org return true; 6545654Sgblack@eecs.umich.edu } 6555704Snate@binkert.org } 6565655Sgblack@eecs.umich.edu return false; 6575655Sgblack@eecs.umich.edu} 6585655Sgblack@eecs.umich.edu 6595655Sgblack@eecs.umich.eduFault 6605689Sgblack@eecs.umich.eduX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 6615655Sgblack@eecs.umich.edu{ 6625655Sgblack@eecs.umich.edu assert(checkInterrupts(tc)); 6635689Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 6645691Sgblack@eecs.umich.edu // check for. 6655655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6665689Sgblack@eecs.umich.edu if (pendingSmi) { 6675691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 6686050Sgblack@eecs.umich.edu return new SystemManagementInterrupt(); 6696050Sgblack@eecs.umich.edu } else if (pendingNmi) { 6706050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 6715655Sgblack@eecs.umich.edu return new NonMaskableInterrupt(nmiVector); 6725655Sgblack@eecs.umich.edu } else if (pendingInit) { 6735655Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 6745655Sgblack@eecs.umich.edu return new InitInterrupt(initVector); 6755655Sgblack@eecs.umich.edu } else if (pendingStartup) { 6765655Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 6775689Sgblack@eecs.umich.edu return new StartupInterrupt(startupVector); 6785691Sgblack@eecs.umich.edu } else { 6795655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 6805689Sgblack@eecs.umich.edu "ints were pending.\n"); 6815655Sgblack@eecs.umich.edu return NoFault; 6825655Sgblack@eecs.umich.edu } 6835655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6845654Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 6855654Sgblack@eecs.umich.edu return new ExternalInterrupt(extIntVector); 6865654Sgblack@eecs.umich.edu } else { 6875704Snate@binkert.org DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 6885654Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 6895704Snate@binkert.org return new ExternalInterrupt(IRRV); 6905655Sgblack@eecs.umich.edu } 6915655Sgblack@eecs.umich.edu} 6925689Sgblack@eecs.umich.edu 6935655Sgblack@eecs.umich.eduvoid 6945655Sgblack@eecs.umich.eduX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 6955689Sgblack@eecs.umich.edu{ 6965655Sgblack@eecs.umich.edu assert(checkInterrupts(tc)); 6975655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6985689Sgblack@eecs.umich.edu if (pendingSmi) { 6995655Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 7006066Sgblack@eecs.umich.edu pendingSmi = false; 7016050Sgblack@eecs.umich.edu } else if (pendingNmi) { 7026050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 7036050Sgblack@eecs.umich.edu pendingNmi = false; 7046066Sgblack@eecs.umich.edu } else if (pendingInit) { 7055655Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 7066050Sgblack@eecs.umich.edu pendingInit = false; 7075655Sgblack@eecs.umich.edu startedUp = false; 7085655Sgblack@eecs.umich.edu } else if (pendingStartup) { 7095655Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SIPI sent to core.\n"); 7105655Sgblack@eecs.umich.edu pendingStartup = false; 7115689Sgblack@eecs.umich.edu startedUp = true; 7125655Sgblack@eecs.umich.edu } 7135655Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 7145655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 7155655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 7165655Sgblack@eecs.umich.edu pendingExtInt = false; 7175655Sgblack@eecs.umich.edu } else { 7185655Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 7195654Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 7205654Sgblack@eecs.umich.edu ISRV = IRRV; 7217902Shestness@cs.utexas.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 7227902Shestness@cs.utexas.edu // Clear it out of the IRR. 7237902Shestness@cs.utexas.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 7247902Shestness@cs.utexas.edu updateIRRV(); 7257902Shestness@cs.utexas.edu } 7267902Shestness@cs.utexas.edu} 7277902Shestness@cs.utexas.edu 7287902Shestness@cs.utexas.eduX86ISA::Interrupts * 7297902Shestness@cs.utexas.eduX86LocalApicParams::create() 7307902Shestness@cs.utexas.edu{ 7317902Shestness@cs.utexas.edu return new X86ISA::Interrupts(this); 7327902Shestness@cs.utexas.edu} 7337902Shestness@cs.utexas.edu