interrupts.cc revision 6046:8ac37d77fa74 
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
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31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63#include "sim/system.hh"
64
65int
66divideFromConf(uint32_t conf)
67{
68    // This figures out what division we want from the division configuration
69    // register in the local APIC. The encoding is a little odd but it can
70    // be deciphered fairly easily.
71    int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
72    shift = (shift + 1) % 8;
73    return 1 << shift;
74}
75
76namespace X86ISA
77{
78
79ApicRegIndex
80decodeAddr(Addr paddr)
81{
82    ApicRegIndex regNum;
83    paddr &= ~mask(3);
84    switch (paddr)
85    {
86      case 0x20:
87        regNum = APIC_ID;
88        break;
89      case 0x30:
90        regNum = APIC_VERSION;
91        break;
92      case 0x80:
93        regNum = APIC_TASK_PRIORITY;
94        break;
95      case 0x90:
96        regNum = APIC_ARBITRATION_PRIORITY;
97        break;
98      case 0xA0:
99        regNum = APIC_PROCESSOR_PRIORITY;
100        break;
101      case 0xB0:
102        regNum = APIC_EOI;
103        break;
104      case 0xD0:
105        regNum = APIC_LOGICAL_DESTINATION;
106        break;
107      case 0xE0:
108        regNum = APIC_DESTINATION_FORMAT;
109        break;
110      case 0xF0:
111        regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
112        break;
113      case 0x100:
114      case 0x108:
115      case 0x110:
116      case 0x118:
117      case 0x120:
118      case 0x128:
119      case 0x130:
120      case 0x138:
121      case 0x140:
122      case 0x148:
123      case 0x150:
124      case 0x158:
125      case 0x160:
126      case 0x168:
127      case 0x170:
128      case 0x178:
129        regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
130        break;
131      case 0x180:
132      case 0x188:
133      case 0x190:
134      case 0x198:
135      case 0x1A0:
136      case 0x1A8:
137      case 0x1B0:
138      case 0x1B8:
139      case 0x1C0:
140      case 0x1C8:
141      case 0x1D0:
142      case 0x1D8:
143      case 0x1E0:
144      case 0x1E8:
145      case 0x1F0:
146      case 0x1F8:
147        regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
148        break;
149      case 0x200:
150      case 0x208:
151      case 0x210:
152      case 0x218:
153      case 0x220:
154      case 0x228:
155      case 0x230:
156      case 0x238:
157      case 0x240:
158      case 0x248:
159      case 0x250:
160      case 0x258:
161      case 0x260:
162      case 0x268:
163      case 0x270:
164      case 0x278:
165        regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
166        break;
167      case 0x280:
168        regNum = APIC_ERROR_STATUS;
169        break;
170      case 0x300:
171        regNum = APIC_INTERRUPT_COMMAND_LOW;
172        break;
173      case 0x310:
174        regNum = APIC_INTERRUPT_COMMAND_HIGH;
175        break;
176      case 0x320:
177        regNum = APIC_LVT_TIMER;
178        break;
179      case 0x330:
180        regNum = APIC_LVT_THERMAL_SENSOR;
181        break;
182      case 0x340:
183        regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
184        break;
185      case 0x350:
186        regNum = APIC_LVT_LINT0;
187        break;
188      case 0x360:
189        regNum = APIC_LVT_LINT1;
190        break;
191      case 0x370:
192        regNum = APIC_LVT_ERROR;
193        break;
194      case 0x380:
195        regNum = APIC_INITIAL_COUNT;
196        break;
197      case 0x390:
198        regNum = APIC_CURRENT_COUNT;
199        break;
200      case 0x3E0:
201        regNum = APIC_DIVIDE_CONFIGURATION;
202        break;
203      default:
204        // A reserved register field.
205        panic("Accessed reserved register field %#x.\n", paddr);
206        break;
207    }
208    return regNum;
209}
210}
211
212Tick
213X86ISA::Interrupts::read(PacketPtr pkt)
214{
215    Addr offset = pkt->getAddr() - pioAddr;
216    //Make sure we're at least only accessing one register.
217    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
218        panic("Accessed more than one register at a time in the APIC!\n");
219    ApicRegIndex reg = decodeAddr(offset);
220    uint32_t val = htog(readReg(reg));
221    DPRINTF(LocalApic,
222            "Reading Local APIC register %d at offset %#x as %#x.\n",
223            reg, offset, val);
224    pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
225    pkt->makeAtomicResponse();
226    return latency;
227}
228
229Tick
230X86ISA::Interrupts::write(PacketPtr pkt)
231{
232    Addr offset = pkt->getAddr() - pioAddr;
233    //Make sure we're at least only accessing one register.
234    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
235        panic("Accessed more than one register at a time in the APIC!\n");
236    ApicRegIndex reg = decodeAddr(offset);
237    uint32_t val = regs[reg];
238    pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
239    DPRINTF(LocalApic,
240            "Writing Local APIC register %d at offset %#x as %#x.\n",
241            reg, offset, gtoh(val));
242    setReg(reg, gtoh(val));
243    pkt->makeAtomicResponse();
244    return latency;
245}
246void
247X86ISA::Interrupts::requestInterrupt(uint8_t vector,
248        uint8_t deliveryMode, bool level)
249{
250    /*
251     * Fixed and lowest-priority delivery mode interrupts are handled
252     * using the IRR/ISR registers, checking against the TPR, etc.
253     * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
254     */
255    if (deliveryMode == DeliveryMode::Fixed ||
256            deliveryMode == DeliveryMode::LowestPriority) {
257        DPRINTF(LocalApic, "Interrupt is an %s.\n",
258                DeliveryMode::names[deliveryMode]);
259        // Queue up the interrupt in the IRR.
260        if (vector > IRRV)
261            IRRV = vector;
262        if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
263            setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
264            if (level) {
265                setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
266            } else {
267                clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
268            }
269        }
270    } else if (!DeliveryMode::isReserved(deliveryMode)) {
271        DPRINTF(LocalApic, "Interrupt is an %s.\n",
272                DeliveryMode::names[deliveryMode]);
273        if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
274            pendingUnmaskableInt = pendingSmi = true;
275            smiVector = vector;
276        } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
277            pendingUnmaskableInt = pendingNmi = true;
278            nmiVector = vector;
279        } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
280            pendingExtInt = true;
281            extIntVector = vector;
282        } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
283            pendingUnmaskableInt = pendingInit = true;
284            initVector = vector;
285        }
286    }
287    cpu->wakeup();
288}
289
290
291void
292X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
293{
294    cpu = newCPU;
295    assert(cpu);
296    regs[APIC_ID] = (cpu->cpuId() << 24);
297}
298
299
300Tick
301X86ISA::Interrupts::recvMessage(PacketPtr pkt)
302{
303    uint8_t id = (regs[APIC_ID] >> 24);
304    Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
305    assert(pkt->cmd == MemCmd::MessageReq);
306    switch(offset)
307    {
308      case 0:
309        {
310            TriggerIntMessage message = pkt->get<TriggerIntMessage>();
311            DPRINTF(LocalApic,
312                    "Got Trigger Interrupt message with vector %#x.\n",
313                    message.vector);
314            // Make sure we're really supposed to get this.
315            assert((message.destMode == 0 && message.destination == id) ||
316                   (bits((int)message.destination, id)));
317
318            requestInterrupt(message.vector,
319                    message.deliveryMode, message.trigger);
320        }
321        break;
322      default:
323        panic("Local apic got unknown interrupt message at offset %#x.\n",
324                offset);
325        break;
326    }
327    delete pkt->req;
328    delete pkt;
329    return latency;
330}
331
332
333void
334X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
335{
336    uint8_t id = (regs[APIC_ID] >> 24);
337    range_list.clear();
338    range_list.push_back(RangeEx(x86LocalAPICAddress(id, 0),
339                                 x86LocalAPICAddress(id, 0) + PageBytes));
340}
341
342
343void
344X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
345{
346    uint8_t id = (regs[APIC_ID] >> 24);
347    range_list.clear();
348    range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
349                x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
350}
351
352
353uint32_t
354X86ISA::Interrupts::readReg(ApicRegIndex reg)
355{
356    if (reg >= APIC_TRIGGER_MODE(0) &&
357            reg <= APIC_TRIGGER_MODE(15)) {
358        panic("Local APIC Trigger Mode registers are unimplemented.\n");
359    }
360    switch (reg) {
361      case APIC_ARBITRATION_PRIORITY:
362        panic("Local APIC Arbitration Priority register unimplemented.\n");
363        break;
364      case APIC_PROCESSOR_PRIORITY:
365        panic("Local APIC Processor Priority register unimplemented.\n");
366        break;
367      case APIC_ERROR_STATUS:
368        regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
369        break;
370      case APIC_CURRENT_COUNT:
371        {
372            if (apicTimerEvent.scheduled()) {
373                assert(clock);
374                // Compute how many m5 ticks happen per count.
375                uint64_t ticksPerCount = clock *
376                    divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
377                // Compute how many m5 ticks are left.
378                uint64_t val = apicTimerEvent.when() - curTick;
379                // Turn that into a count.
380                val = (val + ticksPerCount - 1) / ticksPerCount;
381                return val;
382            } else {
383                return 0;
384            }
385        }
386      default:
387        break;
388    }
389    return regs[reg];
390}
391
392void
393X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
394{
395    uint32_t newVal = val;
396    if (reg >= APIC_IN_SERVICE(0) &&
397            reg <= APIC_IN_SERVICE(15)) {
398        panic("Local APIC In-Service registers are unimplemented.\n");
399    }
400    if (reg >= APIC_TRIGGER_MODE(0) &&
401            reg <= APIC_TRIGGER_MODE(15)) {
402        panic("Local APIC Trigger Mode registers are unimplemented.\n");
403    }
404    if (reg >= APIC_INTERRUPT_REQUEST(0) &&
405            reg <= APIC_INTERRUPT_REQUEST(15)) {
406        panic("Local APIC Interrupt Request registers "
407                "are unimplemented.\n");
408    }
409    switch (reg) {
410      case APIC_ID:
411        newVal = val & 0xFF;
412        break;
413      case APIC_VERSION:
414        // The Local APIC Version register is read only.
415        return;
416      case APIC_TASK_PRIORITY:
417        newVal = val & 0xFF;
418        break;
419      case APIC_ARBITRATION_PRIORITY:
420        panic("Local APIC Arbitration Priority register unimplemented.\n");
421        break;
422      case APIC_PROCESSOR_PRIORITY:
423        panic("Local APIC Processor Priority register unimplemented.\n");
424        break;
425      case APIC_EOI:
426        // Remove the interrupt that just completed from the local apic state.
427        clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
428        updateISRV();
429        return;
430      case APIC_LOGICAL_DESTINATION:
431        newVal = val & 0xFF000000;
432        break;
433      case APIC_DESTINATION_FORMAT:
434        newVal = val | 0x0FFFFFFF;
435        break;
436      case APIC_SPURIOUS_INTERRUPT_VECTOR:
437        regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
438        regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
439        if (val & (1 << 9))
440            warn("Focus processor checking not implemented.\n");
441        break;
442      case APIC_ERROR_STATUS:
443        {
444            if (regs[APIC_INTERNAL_STATE] & 0x1) {
445                regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
446                newVal = 0;
447            } else {
448                regs[APIC_INTERNAL_STATE] |= ULL(0x1);
449                return;
450            }
451
452        }
453        break;
454      case APIC_INTERRUPT_COMMAND_LOW:
455        {
456            InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
457            // Check if we're already sending an IPI.
458            if (low.deliveryStatus) {
459                newVal = low;
460                break;
461            }
462            low = val;
463            InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
464            // Record that an IPI is being sent.
465            low.deliveryStatus = 1;
466            TriggerIntMessage message;
467            message.destination = high.destination;
468            message.vector = low.vector;
469            message.deliveryMode = low.deliveryMode;
470            message.destMode = low.destMode;
471            message.level = low.level;
472            message.trigger = low.trigger;
473            bool timing = sys->getMemoryMode() == Enums::timing;
474            switch (low.destShorthand) {
475              case 0:
476                intPort->sendMessage(message, timing);
477                break;
478              case 1:
479                panic("Self IPIs aren't implemented.\n");
480                break;
481              case 2:
482                panic("Broadcast including self IPIs aren't implemented.\n");
483                break;
484              case 3:
485                panic("Broadcast excluding self IPIs aren't implemented.\n");
486                break;
487            }
488        }
489        break;
490      case APIC_LVT_TIMER:
491      case APIC_LVT_THERMAL_SENSOR:
492      case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
493      case APIC_LVT_LINT0:
494      case APIC_LVT_LINT1:
495      case APIC_LVT_ERROR:
496        {
497            uint64_t readOnlyMask = (1 << 12) | (1 << 14);
498            newVal = (val & ~readOnlyMask) |
499                     (regs[reg] & readOnlyMask);
500        }
501        break;
502      case APIC_INITIAL_COUNT:
503        {
504            assert(clock);
505            newVal = bits(val, 31, 0);
506            // Compute how many timer ticks we're being programmed for.
507            uint64_t newCount = newVal *
508                (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
509            // Schedule on the edge of the next tick plus the new count.
510            Tick offset = curTick % clock;
511            if (offset) {
512                reschedule(apicTimerEvent,
513                        curTick + (newCount + 1) * clock - offset, true);
514            } else {
515                reschedule(apicTimerEvent,
516                        curTick + newCount * clock, true);
517            }
518        }
519        break;
520      case APIC_CURRENT_COUNT:
521        //Local APIC Current Count register is read only.
522        return;
523      case APIC_DIVIDE_CONFIGURATION:
524        newVal = val & 0xB;
525        break;
526      default:
527        break;
528    }
529    regs[reg] = newVal;
530    return;
531}
532
533
534X86ISA::Interrupts::Interrupts(Params * p) :
535    BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
536    apicTimerEvent(this),
537    pendingSmi(false), smiVector(0),
538    pendingNmi(false), nmiVector(0),
539    pendingExtInt(false), extIntVector(0),
540    pendingInit(false), initVector(0),
541    pendingUnmaskableInt(false)
542{
543    pioSize = PageBytes;
544    memset(regs, 0, sizeof(regs));
545    //Set the local apic DFR to the flat model.
546    regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
547    ISRV = 0;
548    IRRV = 0;
549}
550
551
552bool
553X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
554{
555    RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
556    if (pendingUnmaskableInt) {
557        DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
558        return true;
559    }
560    if (rflags.intf) {
561        if (pendingExtInt) {
562            DPRINTF(LocalApic, "Reported pending external interrupt.\n");
563            return true;
564        }
565        if (IRRV > ISRV && bits(IRRV, 7, 4) >
566               bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
567            DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
568            return true;
569        }
570    }
571    return false;
572}
573
574Fault
575X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
576{
577    assert(checkInterrupts(tc));
578    // These are all probably fairly uncommon, so we'll make them easier to
579    // check for.
580    if (pendingUnmaskableInt) {
581        if (pendingSmi) {
582            DPRINTF(LocalApic, "Generated SMI fault object.\n");
583            return new SystemManagementInterrupt();
584        } else if (pendingNmi) {
585            DPRINTF(LocalApic, "Generated NMI fault object.\n");
586            return new NonMaskableInterrupt(nmiVector);
587        } else if (pendingInit) {
588            DPRINTF(LocalApic, "Generated INIT fault object.\n");
589            return new InitInterrupt(initVector);
590        } else {
591            panic("pendingUnmaskableInt set, but no unmaskable "
592                    "ints were pending.\n");
593            return NoFault;
594        }
595    } else if (pendingExtInt) {
596        DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
597        return new ExternalInterrupt(extIntVector);
598    } else {
599        DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
600        // The only thing left are fixed and lowest priority interrupts.
601        return new ExternalInterrupt(IRRV);
602    }
603}
604
605void
606X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
607{
608    assert(checkInterrupts(tc));
609    if (pendingUnmaskableInt) {
610        if (pendingSmi) {
611            DPRINTF(LocalApic, "SMI sent to core.\n");
612            pendingSmi = false;
613        } else if (pendingNmi) {
614            DPRINTF(LocalApic, "NMI sent to core.\n");
615            pendingNmi = false;
616        } else if (pendingInit) {
617            DPRINTF(LocalApic, "Init sent to core.\n");
618            pendingInit = false;
619        }
620        if (!(pendingSmi || pendingNmi || pendingInit))
621            pendingUnmaskableInt = false;
622    } else if (pendingExtInt) {
623        pendingExtInt = false;
624    } else {
625        DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
626        // Mark the interrupt as "in service".
627        ISRV = IRRV;
628        setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
629        // Clear it out of the IRR.
630        clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
631        updateIRRV();
632    }
633}
634
635X86ISA::Interrupts *
636X86LocalApicParams::create()
637{
638    return new X86ISA::Interrupts(this);
639}
640