interrupts.cc revision 5654:340254de2031
13560SN/A/* 23560SN/A * Copyright (c) 2008 The Hewlett-Packard Development Company 33560SN/A * All rights reserved. 43560SN/A * 53560SN/A * Redistribution and use of this software in source and binary forms, 63560SN/A * with or without modification, are permitted provided that the 73560SN/A * following conditions are met: 83560SN/A * 93560SN/A * The software must be used only for Non-Commercial Use which means any 103560SN/A * use which is NOT directed to receiving any direct monetary 113560SN/A * compensation for, or commercial advantage from such use. Illustrative 123560SN/A * examples of non-commercial use are academic research, personal study, 133560SN/A * teaching, education and corporate research & development. 143560SN/A * Illustrative examples of commercial use are distributing products for 153560SN/A * commercial advantage and providing services using the software for 163560SN/A * commercial advantage. 173560SN/A * 183560SN/A * If you wish to use this software or functionality therein that may be 193560SN/A * covered by patents for commercial use, please contact: 203560SN/A * Director of Intellectual Property Licensing 213560SN/A * Office of Strategy and Technology 223560SN/A * Hewlett-Packard Company 233560SN/A * 1501 Page Mill Road 243560SN/A * Palo Alto, California 94304 253560SN/A * 263560SN/A * Redistributions of source code must retain the above copyright notice, 273560SN/A * this list of conditions and the following disclaimer. Redistributions 283560SN/A * in binary form must reproduce the above copyright notice, this list of 293560SN/A * conditions and the following disclaimer in the documentation and/or 303560SN/A * other materials provided with the distribution. Neither the name of 313560SN/A * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 323560SN/A * contributors may be used to endorse or promote products derived from 333560SN/A * this software without specific prior written permission. No right of 343560SN/A * sublicense is granted herewith. Derivatives of the software and 353560SN/A * output created using the software may be prepared, but only for 363560SN/A * Non-Commercial Uses. Derivatives of the software may be shared with 373560SN/A * others provided: (i) the others agree to abide by the list of 383560SN/A * conditions herein which includes the Non-Commercial Use restrictions; 393560SN/A * and (ii) such Derivatives of the software include the above copyright 403560SN/A * notice to acknowledge the contribution from this software where 413565Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 423560SN/A * 433560SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 443560SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 453560SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 463560SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 473560SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 483560SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 493560SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 503560SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 513560SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 523560SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 533560SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 543560SN/A * 553560SN/A * Authors: Gabe Black 563560SN/A */ 573560SN/A 583560SN/A#include "arch/x86/apicregs.hh" 593560SN/A#include "arch/x86/interrupts.hh" 603560SN/A#include "arch/x86/intmessage.hh" 615999Snate@binkert.org#include "cpu/base.hh" 625999Snate@binkert.org#include "mem/packet_access.hh" 633560SN/A 645999Snate@binkert.orgint 655999Snate@binkert.orgdivideFromConf(uint32_t conf) 663560SN/A{ 675999Snate@binkert.org // This figures out what division we want from the division configuration 683560SN/A // register in the local APIC. The encoding is a little odd but it can 695999Snate@binkert.org // be deciphered fairly easily. 703560SN/A int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 713560SN/A shift = (shift + 1) % 8; 7212181Sgabeblack@google.com return 1 << shift; 733560SN/A} 743560SN/A 753560SN/Anamespace X86ISA 763560SN/A{ 773560SN/A 783560SN/AApicRegIndex 793560SN/AdecodeAddr(Addr paddr) 803560SN/A{ 813560SN/A ApicRegIndex regNum; 823560SN/A paddr &= ~mask(3); 833560SN/A switch (paddr) 843560SN/A { 8511168Sandreas.hansson@arm.com case 0x20: 8611168Sandreas.hansson@arm.com regNum = APIC_ID; 873560SN/A break; 883560SN/A case 0x30: 895568Snate@binkert.org regNum = APIC_VERSION; 905568Snate@binkert.org break; 913560SN/A case 0x80: 923560SN/A regNum = APIC_TASK_PRIORITY; 93 break; 94 case 0x90: 95 regNum = APIC_ARBITRATION_PRIORITY; 96 break; 97 case 0xA0: 98 regNum = APIC_PROCESSOR_PRIORITY; 99 break; 100 case 0xB0: 101 regNum = APIC_EOI; 102 break; 103 case 0xD0: 104 regNum = APIC_LOGICAL_DESTINATION; 105 break; 106 case 0xE0: 107 regNum = APIC_DESTINATION_FORMAT; 108 break; 109 case 0xF0: 110 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 111 break; 112 case 0x100: 113 case 0x108: 114 case 0x110: 115 case 0x118: 116 case 0x120: 117 case 0x128: 118 case 0x130: 119 case 0x138: 120 case 0x140: 121 case 0x148: 122 case 0x150: 123 case 0x158: 124 case 0x160: 125 case 0x168: 126 case 0x170: 127 case 0x178: 128 regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 129 break; 130 case 0x180: 131 case 0x188: 132 case 0x190: 133 case 0x198: 134 case 0x1A0: 135 case 0x1A8: 136 case 0x1B0: 137 case 0x1B8: 138 case 0x1C0: 139 case 0x1C8: 140 case 0x1D0: 141 case 0x1D8: 142 case 0x1E0: 143 case 0x1E8: 144 case 0x1F0: 145 case 0x1F8: 146 regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 147 break; 148 case 0x200: 149 case 0x208: 150 case 0x210: 151 case 0x218: 152 case 0x220: 153 case 0x228: 154 case 0x230: 155 case 0x238: 156 case 0x240: 157 case 0x248: 158 case 0x250: 159 case 0x258: 160 case 0x260: 161 case 0x268: 162 case 0x270: 163 case 0x278: 164 regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 165 break; 166 case 0x280: 167 regNum = APIC_ERROR_STATUS; 168 break; 169 case 0x300: 170 regNum = APIC_INTERRUPT_COMMAND_LOW; 171 break; 172 case 0x310: 173 regNum = APIC_INTERRUPT_COMMAND_HIGH; 174 break; 175 case 0x320: 176 regNum = APIC_LVT_TIMER; 177 break; 178 case 0x330: 179 regNum = APIC_LVT_THERMAL_SENSOR; 180 break; 181 case 0x340: 182 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 183 break; 184 case 0x350: 185 regNum = APIC_LVT_LINT0; 186 break; 187 case 0x360: 188 regNum = APIC_LVT_LINT1; 189 break; 190 case 0x370: 191 regNum = APIC_LVT_ERROR; 192 break; 193 case 0x380: 194 regNum = APIC_INITIAL_COUNT; 195 break; 196 case 0x390: 197 regNum = APIC_CURRENT_COUNT; 198 break; 199 case 0x3E0: 200 regNum = APIC_DIVIDE_CONFIGURATION; 201 break; 202 default: 203 // A reserved register field. 204 panic("Accessed reserved register field %#x.\n", paddr); 205 break; 206 } 207 return regNum; 208} 209} 210 211Tick 212X86ISA::Interrupts::read(PacketPtr pkt) 213{ 214 Addr offset = pkt->getAddr() - pioAddr; 215 //Make sure we're at least only accessing one register. 216 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 217 panic("Accessed more than one register at a time in the APIC!\n"); 218 ApicRegIndex reg = decodeAddr(offset); 219 uint32_t val = htog(readReg(reg)); 220 DPRINTF(LocalApic, 221 "Reading Local APIC register %d at offset %#x as %#x.\n", 222 reg, offset, val); 223 pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 224 return latency; 225} 226 227Tick 228X86ISA::Interrupts::write(PacketPtr pkt) 229{ 230 Addr offset = pkt->getAddr() - pioAddr; 231 //Make sure we're at least only accessing one register. 232 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 233 panic("Accessed more than one register at a time in the APIC!\n"); 234 ApicRegIndex reg = decodeAddr(offset); 235 uint32_t val = regs[reg]; 236 pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 237 DPRINTF(LocalApic, 238 "Writing Local APIC register %d at offset %#x as %#x.\n", 239 reg, offset, gtoh(val)); 240 setReg(reg, gtoh(val)); 241 return latency; 242} 243 244Tick 245X86ISA::Interrupts::recvMessage(PacketPtr pkt) 246{ 247 uint8_t id = 0; 248 Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0); 249 assert(pkt->cmd == MemCmd::MessageReq); 250 switch(offset) 251 { 252 case 0: 253 { 254 TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 255 uint8_t vector = message.vector; 256 DPRINTF(LocalApic, 257 "Got Trigger Interrupt message with vector %#x.\n", 258 vector); 259 // Make sure we're really supposed to get this. 260 assert((message.destMode == 0 && message.destination == id) || 261 (bits((int)message.destination, id))); 262 if (DeliveryMode::isUnmaskable(message.deliveryMode)) { 263 DPRINTF(LocalApic, "Interrupt is an %s and unmaskable.\n", 264 DeliveryMode::names[message.deliveryMode]); 265 panic("Unmaskable interrupts aren't implemented.\n"); 266 } else if (DeliveryMode::isMaskable(message.deliveryMode)) { 267 DPRINTF(LocalApic, "Interrupt is an %s and maskable.\n", 268 DeliveryMode::names[message.deliveryMode]); 269 // Queue up the interrupt in the IRR. 270 if (vector > IRRV) 271 IRRV = vector; 272 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 273 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 274 if (message.trigger) { 275 // Level triggered. 276 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 277 } else { 278 // Edge triggered. 279 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 280 } 281 } 282 } 283 } 284 break; 285 default: 286 panic("Local apic got unknown interrupt message at offset %#x.\n", 287 offset); 288 break; 289 } 290 delete pkt->req; 291 delete pkt; 292 return latency; 293} 294 295 296uint32_t 297X86ISA::Interrupts::readReg(ApicRegIndex reg) 298{ 299 if (reg >= APIC_TRIGGER_MODE(0) && 300 reg <= APIC_TRIGGER_MODE(15)) { 301 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 302 } 303 switch (reg) { 304 case APIC_ARBITRATION_PRIORITY: 305 panic("Local APIC Arbitration Priority register unimplemented.\n"); 306 break; 307 case APIC_PROCESSOR_PRIORITY: 308 panic("Local APIC Processor Priority register unimplemented.\n"); 309 break; 310 case APIC_EOI: 311 panic("Local APIC EOI register unimplemented.\n"); 312 break; 313 case APIC_ERROR_STATUS: 314 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 315 break; 316 case APIC_INTERRUPT_COMMAND_LOW: 317 panic("Local APIC Interrupt Command low" 318 " register unimplemented.\n"); 319 break; 320 case APIC_INTERRUPT_COMMAND_HIGH: 321 panic("Local APIC Interrupt Command high" 322 " register unimplemented.\n"); 323 break; 324 case APIC_CURRENT_COUNT: 325 { 326 assert(clock); 327 uint32_t val = regs[reg] - curTick / clock; 328 val /= (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 329 return val; 330 } 331 default: 332 break; 333 } 334 return regs[reg]; 335} 336 337void 338X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 339{ 340 uint32_t newVal = val; 341 if (reg >= APIC_IN_SERVICE(0) && 342 reg <= APIC_IN_SERVICE(15)) { 343 panic("Local APIC In-Service registers are unimplemented.\n"); 344 } 345 if (reg >= APIC_TRIGGER_MODE(0) && 346 reg <= APIC_TRIGGER_MODE(15)) { 347 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 348 } 349 if (reg >= APIC_INTERRUPT_REQUEST(0) && 350 reg <= APIC_INTERRUPT_REQUEST(15)) { 351 panic("Local APIC Interrupt Request registers " 352 "are unimplemented.\n"); 353 } 354 switch (reg) { 355 case APIC_ID: 356 newVal = val & 0xFF; 357 break; 358 case APIC_VERSION: 359 // The Local APIC Version register is read only. 360 return; 361 case APIC_TASK_PRIORITY: 362 newVal = val & 0xFF; 363 break; 364 case APIC_ARBITRATION_PRIORITY: 365 panic("Local APIC Arbitration Priority register unimplemented.\n"); 366 break; 367 case APIC_PROCESSOR_PRIORITY: 368 panic("Local APIC Processor Priority register unimplemented.\n"); 369 break; 370 case APIC_EOI: 371 panic("Local APIC EOI register unimplemented.\n"); 372 break; 373 case APIC_LOGICAL_DESTINATION: 374 newVal = val & 0xFF000000; 375 break; 376 case APIC_DESTINATION_FORMAT: 377 newVal = val | 0x0FFFFFFF; 378 break; 379 case APIC_SPURIOUS_INTERRUPT_VECTOR: 380 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 381 regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 382 if (val & (1 << 9)) 383 warn("Focus processor checking not implemented.\n"); 384 break; 385 case APIC_ERROR_STATUS: 386 { 387 if (regs[APIC_INTERNAL_STATE] & 0x1) { 388 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 389 newVal = 0; 390 } else { 391 regs[APIC_INTERNAL_STATE] |= ULL(0x1); 392 return; 393 } 394 395 } 396 break; 397 case APIC_INTERRUPT_COMMAND_LOW: 398 panic("Local APIC Interrupt Command low" 399 " register unimplemented.\n"); 400 break; 401 case APIC_INTERRUPT_COMMAND_HIGH: 402 panic("Local APIC Interrupt Command high" 403 " register unimplemented.\n"); 404 break; 405 case APIC_LVT_TIMER: 406 case APIC_LVT_THERMAL_SENSOR: 407 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 408 case APIC_LVT_LINT0: 409 case APIC_LVT_LINT1: 410 case APIC_LVT_ERROR: 411 { 412 uint64_t readOnlyMask = (1 << 12) | (1 << 14); 413 newVal = (val & ~readOnlyMask) | 414 (regs[reg] & readOnlyMask); 415 } 416 break; 417 case APIC_INITIAL_COUNT: 418 { 419 assert(clock); 420 newVal = bits(val, 31, 0); 421 uint32_t newCount = newVal * 422 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]) * 16); 423 regs[APIC_CURRENT_COUNT] = newCount + curTick / clock; 424 // Find out how long a "tick" of the timer should take. 425 Tick timerTick = 16 * clock; 426 // Schedule on the edge of the next tick plus the new count. 427 Tick offset = curTick % timerTick; 428 if (offset) { 429 reschedule(apicTimerEvent, 430 curTick + (newCount + 1) * timerTick - offset, true); 431 } else { 432 reschedule(apicTimerEvent, 433 curTick + newCount * timerTick, true); 434 } 435 } 436 break; 437 case APIC_CURRENT_COUNT: 438 //Local APIC Current Count register is read only. 439 return; 440 case APIC_DIVIDE_CONFIGURATION: 441 newVal = val & 0xB; 442 break; 443 default: 444 break; 445 } 446 regs[reg] = newVal; 447 return; 448} 449 450bool 451X86ISA::Interrupts::check_interrupts(ThreadContext * tc) const 452{ 453 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 454 if (IRRV > ISRV && rflags.intf && 455 bits(IRRV, 7, 4) > bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 456 return true; 457 } 458 return false; 459} 460 461Fault 462X86ISA::Interrupts::getInterrupt(ThreadContext * tc) 463{ 464 assert(check_interrupts(tc)); 465 return new ExternalInterrupt(IRRV); 466} 467 468void 469X86ISA::Interrupts::updateIntrInfo(ThreadContext * tc) 470{ 471 assert(check_interrupts(tc)); 472 // Mark the interrupt as "in service". 473 ISRV = IRRV; 474 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 475 // Clear it out of the IRR. 476 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 477 updateIRRV(); 478} 479 480X86ISA::Interrupts * 481X86LocalApicParams::create() 482{ 483 return new X86ISA::Interrupts(this); 484} 485