interrupts.cc revision 6136
19342SAndreas.Sandberg@arm.com/* 210910Sandreas.sandberg@arm.com * Copyright (c) 2008 The Hewlett-Packard Development Company 39342SAndreas.Sandberg@arm.com * All rights reserved. 49342SAndreas.Sandberg@arm.com * 59342SAndreas.Sandberg@arm.com * Redistribution and use of this software in source and binary forms, 69342SAndreas.Sandberg@arm.com * with or without modification, are permitted provided that the 79342SAndreas.Sandberg@arm.com * following conditions are met: 89342SAndreas.Sandberg@arm.com * 99342SAndreas.Sandberg@arm.com * The software must be used only for Non-Commercial Use which means any 109342SAndreas.Sandberg@arm.com * use which is NOT directed to receiving any direct monetary 119342SAndreas.Sandberg@arm.com * compensation for, or commercial advantage from such use. Illustrative 129342SAndreas.Sandberg@arm.com * examples of non-commercial use are academic research, personal study, 139342SAndreas.Sandberg@arm.com * teaching, education and corporate research & development. 149342SAndreas.Sandberg@arm.com * Illustrative examples of commercial use are distributing products for 159342SAndreas.Sandberg@arm.com * commercial advantage and providing services using the software for 169342SAndreas.Sandberg@arm.com * commercial advantage. 179342SAndreas.Sandberg@arm.com * 189342SAndreas.Sandberg@arm.com * If you wish to use this software or functionality therein that may be 199342SAndreas.Sandberg@arm.com * covered by patents for commercial use, please contact: 209342SAndreas.Sandberg@arm.com * Director of Intellectual Property Licensing 219342SAndreas.Sandberg@arm.com * Office of Strategy and Technology 229342SAndreas.Sandberg@arm.com * Hewlett-Packard Company 239342SAndreas.Sandberg@arm.com * 1501 Page Mill Road 249342SAndreas.Sandberg@arm.com * Palo Alto, California 94304 259342SAndreas.Sandberg@arm.com * 269342SAndreas.Sandberg@arm.com * Redistributions of source code must retain the above copyright notice, 279342SAndreas.Sandberg@arm.com * this list of conditions and the following disclaimer. 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Derivatives of the software may be shared with 379342SAndreas.Sandberg@arm.com * others provided: (i) the others agree to abide by the list of 389342SAndreas.Sandberg@arm.com * conditions herein which includes the Non-Commercial Use restrictions; 399342SAndreas.Sandberg@arm.com * and (ii) such Derivatives of the software include the above copyright 409342SAndreas.Sandberg@arm.com * notice to acknowledge the contribution from this software where 4110912Sandreas.sandberg@arm.com * applicable, this list of conditions and the disclaimer below. 4210912Sandreas.sandberg@arm.com * 4310912Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 4410912Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 459342SAndreas.Sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 4611417Ssascha.bischoff@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 479342SAndreas.Sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 4810912Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 4910912Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 509342SAndreas.Sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 5110912Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 5210912Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 539342SAndreas.Sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 549342SAndreas.Sandberg@arm.com * 559342SAndreas.Sandberg@arm.com * Authors: Gabe Black 569342SAndreas.Sandberg@arm.com */ 579342SAndreas.Sandberg@arm.com 589342SAndreas.Sandberg@arm.com#include "arch/x86/apicregs.hh" 599342SAndreas.Sandberg@arm.com#include "arch/x86/interrupts.hh" 6010912Sandreas.sandberg@arm.com#include "arch/x86/intmessage.hh" 6110912Sandreas.sandberg@arm.com#include "cpu/base.hh" 629342SAndreas.Sandberg@arm.com#include "mem/packet_access.hh" 6310912Sandreas.sandberg@arm.com#include "sim/system.hh" 6410912Sandreas.sandberg@arm.com 6510912Sandreas.sandberg@arm.comint 6610912Sandreas.sandberg@arm.comdivideFromConf(uint32_t conf) 6710912Sandreas.sandberg@arm.com{ 6810912Sandreas.sandberg@arm.com // This figures out what division we want from the division configuration 6910912Sandreas.sandberg@arm.com // register in the local APIC. The encoding is a little odd but it can 7010912Sandreas.sandberg@arm.com // be deciphered fairly easily. 7111417Ssascha.bischoff@arm.com int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 7211417Ssascha.bischoff@arm.com shift = (shift + 1) % 8; 7311417Ssascha.bischoff@arm.com return 1 << shift; 7411417Ssascha.bischoff@arm.com} 7511417Ssascha.bischoff@arm.com 7611417Ssascha.bischoff@arm.comnamespace X86ISA 7711417Ssascha.bischoff@arm.com{ 7811417Ssascha.bischoff@arm.com 7911417Ssascha.bischoff@arm.comApicRegIndex 8010912Sandreas.sandberg@arm.comdecodeAddr(Addr paddr) 8110912Sandreas.sandberg@arm.com{ 8210912Sandreas.sandberg@arm.com ApicRegIndex regNum; 8310912Sandreas.sandberg@arm.com paddr &= ~mask(3); 8410912Sandreas.sandberg@arm.com switch (paddr) 8510912Sandreas.sandberg@arm.com { 8610912Sandreas.sandberg@arm.com case 0x20: 8710912Sandreas.sandberg@arm.com regNum = APIC_ID; 8810912Sandreas.sandberg@arm.com break; 8910912Sandreas.sandberg@arm.com case 0x30: 909342SAndreas.Sandberg@arm.com regNum = APIC_VERSION; 919342SAndreas.Sandberg@arm.com break; 9210912Sandreas.sandberg@arm.com case 0x80: 9310912Sandreas.sandberg@arm.com regNum = APIC_TASK_PRIORITY; 9410912Sandreas.sandberg@arm.com break; 9510912Sandreas.sandberg@arm.com case 0x90: 9610912Sandreas.sandberg@arm.com regNum = APIC_ARBITRATION_PRIORITY; 9710912Sandreas.sandberg@arm.com break; 9810912Sandreas.sandberg@arm.com case 0xA0: 9910912Sandreas.sandberg@arm.com regNum = APIC_PROCESSOR_PRIORITY; 10010912Sandreas.sandberg@arm.com break; 10110912Sandreas.sandberg@arm.com case 0xB0: 10210912Sandreas.sandberg@arm.com regNum = APIC_EOI; 10310912Sandreas.sandberg@arm.com break; 10410912Sandreas.sandberg@arm.com case 0xD0: 10510912Sandreas.sandberg@arm.com regNum = APIC_LOGICAL_DESTINATION; 10610912Sandreas.sandberg@arm.com break; 10710912Sandreas.sandberg@arm.com case 0xE0: 10810912Sandreas.sandberg@arm.com regNum = APIC_DESTINATION_FORMAT; 10910913Sandreas.sandberg@arm.com break; 11010912Sandreas.sandberg@arm.com case 0xF0: 11110912Sandreas.sandberg@arm.com regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 11210912Sandreas.sandberg@arm.com break; 11310912Sandreas.sandberg@arm.com case 0x100: 11410912Sandreas.sandberg@arm.com case 0x108: 11510912Sandreas.sandberg@arm.com case 0x110: 11610912Sandreas.sandberg@arm.com case 0x118: 11710912Sandreas.sandberg@arm.com case 0x120: 11810912Sandreas.sandberg@arm.com case 0x128: 11910912Sandreas.sandberg@arm.com case 0x130: 12010912Sandreas.sandberg@arm.com case 0x138: 12110912Sandreas.sandberg@arm.com case 0x140: 12210912Sandreas.sandberg@arm.com case 0x148: 12310912Sandreas.sandberg@arm.com case 0x150: 12410912Sandreas.sandberg@arm.com case 0x158: 12510912Sandreas.sandberg@arm.com case 0x160: 12610912Sandreas.sandberg@arm.com case 0x168: 12710912Sandreas.sandberg@arm.com case 0x170: 12810912Sandreas.sandberg@arm.com case 0x178: 12910912Sandreas.sandberg@arm.com regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 13010912Sandreas.sandberg@arm.com break; 13110912Sandreas.sandberg@arm.com case 0x180: 13210912Sandreas.sandberg@arm.com case 0x188: 13310912Sandreas.sandberg@arm.com case 0x190: 13410912Sandreas.sandberg@arm.com case 0x198: 13510912Sandreas.sandberg@arm.com case 0x1A0: 13610912Sandreas.sandberg@arm.com case 0x1A8: 13710912Sandreas.sandberg@arm.com case 0x1B0: 13810912Sandreas.sandberg@arm.com case 0x1B8: 13910912Sandreas.sandberg@arm.com case 0x1C0: 14010912Sandreas.sandberg@arm.com case 0x1C8: 14110912Sandreas.sandberg@arm.com case 0x1D0: 14210912Sandreas.sandberg@arm.com case 0x1D8: 14310912Sandreas.sandberg@arm.com case 0x1E0: 14410912Sandreas.sandberg@arm.com case 0x1E8: 14510912Sandreas.sandberg@arm.com case 0x1F0: 14610912Sandreas.sandberg@arm.com case 0x1F8: 14710912Sandreas.sandberg@arm.com regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 14810912Sandreas.sandberg@arm.com break; 14910912Sandreas.sandberg@arm.com case 0x200: 15010912Sandreas.sandberg@arm.com case 0x208: 15110912Sandreas.sandberg@arm.com case 0x210: 15210912Sandreas.sandberg@arm.com case 0x218: 15310912Sandreas.sandberg@arm.com case 0x220: 15410912Sandreas.sandberg@arm.com case 0x228: 15510912Sandreas.sandberg@arm.com case 0x230: 15610912Sandreas.sandberg@arm.com case 0x238: 1579342SAndreas.Sandberg@arm.com case 0x240: 1589342SAndreas.Sandberg@arm.com case 0x248: 1599342SAndreas.Sandberg@arm.com case 0x250: 16010912Sandreas.sandberg@arm.com case 0x258: 16110998Sandreas.sandberg@arm.com case 0x260: 1629342SAndreas.Sandberg@arm.com case 0x268: 16310912Sandreas.sandberg@arm.com case 0x270: 1649342SAndreas.Sandberg@arm.com case 0x278: 1659342SAndreas.Sandberg@arm.com regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1669342SAndreas.Sandberg@arm.com break; 1679342SAndreas.Sandberg@arm.com case 0x280: 16810912Sandreas.sandberg@arm.com regNum = APIC_ERROR_STATUS; 1699342SAndreas.Sandberg@arm.com break; 1709342SAndreas.Sandberg@arm.com case 0x300: 17110913Sandreas.sandberg@arm.com regNum = APIC_INTERRUPT_COMMAND_LOW; 17210913Sandreas.sandberg@arm.com break; 17310913Sandreas.sandberg@arm.com case 0x310: 17410913Sandreas.sandberg@arm.com regNum = APIC_INTERRUPT_COMMAND_HIGH; 17510913Sandreas.sandberg@arm.com break; 17610913Sandreas.sandberg@arm.com case 0x320: 17710913Sandreas.sandberg@arm.com regNum = APIC_LVT_TIMER; 17810913Sandreas.sandberg@arm.com break; 17910913Sandreas.sandberg@arm.com case 0x330: 18010913Sandreas.sandberg@arm.com regNum = APIC_LVT_THERMAL_SENSOR; 18110913Sandreas.sandberg@arm.com break; 1829342SAndreas.Sandberg@arm.com case 0x340: 18310913Sandreas.sandberg@arm.com regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1849342SAndreas.Sandberg@arm.com break; 18510913Sandreas.sandberg@arm.com case 0x350: 18610913Sandreas.sandberg@arm.com regNum = APIC_LVT_LINT0; 18710913Sandreas.sandberg@arm.com break; 18810910Sandreas.sandberg@arm.com case 0x360: 18910913Sandreas.sandberg@arm.com regNum = APIC_LVT_LINT1; 1909342SAndreas.Sandberg@arm.com break; 191 case 0x370: 192 regNum = APIC_LVT_ERROR; 193 break; 194 case 0x380: 195 regNum = APIC_INITIAL_COUNT; 196 break; 197 case 0x390: 198 regNum = APIC_CURRENT_COUNT; 199 break; 200 case 0x3E0: 201 regNum = APIC_DIVIDE_CONFIGURATION; 202 break; 203 default: 204 // A reserved register field. 205 panic("Accessed reserved register field %#x.\n", paddr); 206 break; 207 } 208 return regNum; 209} 210} 211 212Tick 213X86ISA::Interrupts::read(PacketPtr pkt) 214{ 215 Addr offset = pkt->getAddr() - pioAddr; 216 //Make sure we're at least only accessing one register. 217 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 218 panic("Accessed more than one register at a time in the APIC!\n"); 219 ApicRegIndex reg = decodeAddr(offset); 220 uint32_t val = htog(readReg(reg)); 221 DPRINTF(LocalApic, 222 "Reading Local APIC register %d at offset %#x as %#x.\n", 223 reg, offset, val); 224 pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 225 pkt->makeAtomicResponse(); 226 return latency; 227} 228 229Tick 230X86ISA::Interrupts::write(PacketPtr pkt) 231{ 232 Addr offset = pkt->getAddr() - pioAddr; 233 //Make sure we're at least only accessing one register. 234 if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 235 panic("Accessed more than one register at a time in the APIC!\n"); 236 ApicRegIndex reg = decodeAddr(offset); 237 uint32_t val = regs[reg]; 238 pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 239 DPRINTF(LocalApic, 240 "Writing Local APIC register %d at offset %#x as %#x.\n", 241 reg, offset, gtoh(val)); 242 setReg(reg, gtoh(val)); 243 pkt->makeAtomicResponse(); 244 return latency; 245} 246void 247X86ISA::Interrupts::requestInterrupt(uint8_t vector, 248 uint8_t deliveryMode, bool level) 249{ 250 /* 251 * Fixed and lowest-priority delivery mode interrupts are handled 252 * using the IRR/ISR registers, checking against the TPR, etc. 253 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 254 */ 255 if (deliveryMode == DeliveryMode::Fixed || 256 deliveryMode == DeliveryMode::LowestPriority) { 257 DPRINTF(LocalApic, "Interrupt is an %s.\n", 258 DeliveryMode::names[deliveryMode]); 259 // Queue up the interrupt in the IRR. 260 if (vector > IRRV) 261 IRRV = vector; 262 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 263 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 264 if (level) { 265 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 266 } else { 267 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 268 } 269 } 270 } else if (!DeliveryMode::isReserved(deliveryMode)) { 271 DPRINTF(LocalApic, "Interrupt is an %s.\n", 272 DeliveryMode::names[deliveryMode]); 273 if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 274 pendingUnmaskableInt = pendingSmi = true; 275 smiVector = vector; 276 } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 277 pendingUnmaskableInt = pendingNmi = true; 278 nmiVector = vector; 279 } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 280 pendingExtInt = true; 281 extIntVector = vector; 282 } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 283 pendingUnmaskableInt = pendingInit = true; 284 initVector = vector; 285 } else if (deliveryMode == DeliveryMode::SIPI && 286 !pendingStartup && !startedUp) { 287 pendingUnmaskableInt = pendingStartup = true; 288 startupVector = vector; 289 } 290 } 291 cpu->wakeup(); 292} 293 294 295void 296X86ISA::Interrupts::setCPU(BaseCPU * newCPU) 297{ 298 assert(newCPU); 299 if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 300 panic("Local APICs can't be moved between CPUs" 301 " with different IDs.\n"); 302 } 303 cpu = newCPU; 304 initialApicId = cpu->cpuId(); 305 regs[APIC_ID] = (initialApicId << 24); 306} 307 308 309Tick 310X86ISA::Interrupts::recvMessage(PacketPtr pkt) 311{ 312 Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 313 assert(pkt->cmd == MemCmd::MessageReq); 314 switch(offset) 315 { 316 case 0: 317 { 318 TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 319 DPRINTF(LocalApic, 320 "Got Trigger Interrupt message with vector %#x.\n", 321 message.vector); 322 323 requestInterrupt(message.vector, 324 message.deliveryMode, message.trigger); 325 } 326 break; 327 default: 328 panic("Local apic got unknown interrupt message at offset %#x.\n", 329 offset); 330 break; 331 } 332 pkt->makeAtomicResponse(); 333 return latency; 334} 335 336 337Tick 338X86ISA::Interrupts::recvResponse(PacketPtr pkt) 339{ 340 assert(!pkt->isError()); 341 assert(pkt->cmd == MemCmd::MessageResp); 342 if (--pendingIPIs == 0) { 343 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 344 // Record that the ICR is now idle. 345 low.deliveryStatus = 0; 346 regs[APIC_INTERRUPT_COMMAND_LOW] = low; 347 } 348 delete pkt->req; 349 delete pkt; 350 DPRINTF(LocalApic, "ICR is now idle.\n"); 351 return 0; 352} 353 354 355void 356X86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 357{ 358 range_list.clear(); 359 Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0), 360 x86LocalAPICAddress(initialApicId, 0) + 361 PageBytes); 362 range_list.push_back(range); 363 pioAddr = range.start; 364} 365 366 367void 368X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 369{ 370 range_list.clear(); 371 range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 372 x86InterruptAddress(initialApicId, 0) + 373 PhysAddrAPICRangeSize)); 374} 375 376 377uint32_t 378X86ISA::Interrupts::readReg(ApicRegIndex reg) 379{ 380 if (reg >= APIC_TRIGGER_MODE(0) && 381 reg <= APIC_TRIGGER_MODE(15)) { 382 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 383 } 384 switch (reg) { 385 case APIC_ARBITRATION_PRIORITY: 386 panic("Local APIC Arbitration Priority register unimplemented.\n"); 387 break; 388 case APIC_PROCESSOR_PRIORITY: 389 panic("Local APIC Processor Priority register unimplemented.\n"); 390 break; 391 case APIC_ERROR_STATUS: 392 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 393 break; 394 case APIC_CURRENT_COUNT: 395 { 396 if (apicTimerEvent.scheduled()) { 397 assert(clock); 398 // Compute how many m5 ticks happen per count. 399 uint64_t ticksPerCount = clock * 400 divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 401 // Compute how many m5 ticks are left. 402 uint64_t val = apicTimerEvent.when() - curTick; 403 // Turn that into a count. 404 val = (val + ticksPerCount - 1) / ticksPerCount; 405 return val; 406 } else { 407 return 0; 408 } 409 } 410 default: 411 break; 412 } 413 return regs[reg]; 414} 415 416void 417X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 418{ 419 uint32_t newVal = val; 420 if (reg >= APIC_IN_SERVICE(0) && 421 reg <= APIC_IN_SERVICE(15)) { 422 panic("Local APIC In-Service registers are unimplemented.\n"); 423 } 424 if (reg >= APIC_TRIGGER_MODE(0) && 425 reg <= APIC_TRIGGER_MODE(15)) { 426 panic("Local APIC Trigger Mode registers are unimplemented.\n"); 427 } 428 if (reg >= APIC_INTERRUPT_REQUEST(0) && 429 reg <= APIC_INTERRUPT_REQUEST(15)) { 430 panic("Local APIC Interrupt Request registers " 431 "are unimplemented.\n"); 432 } 433 switch (reg) { 434 case APIC_ID: 435 newVal = val & 0xFF; 436 break; 437 case APIC_VERSION: 438 // The Local APIC Version register is read only. 439 return; 440 case APIC_TASK_PRIORITY: 441 newVal = val & 0xFF; 442 break; 443 case APIC_ARBITRATION_PRIORITY: 444 panic("Local APIC Arbitration Priority register unimplemented.\n"); 445 break; 446 case APIC_PROCESSOR_PRIORITY: 447 panic("Local APIC Processor Priority register unimplemented.\n"); 448 break; 449 case APIC_EOI: 450 // Remove the interrupt that just completed from the local apic state. 451 clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 452 updateISRV(); 453 return; 454 case APIC_LOGICAL_DESTINATION: 455 newVal = val & 0xFF000000; 456 break; 457 case APIC_DESTINATION_FORMAT: 458 newVal = val | 0x0FFFFFFF; 459 break; 460 case APIC_SPURIOUS_INTERRUPT_VECTOR: 461 regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 462 regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 463 if (val & (1 << 9)) 464 warn("Focus processor checking not implemented.\n"); 465 break; 466 case APIC_ERROR_STATUS: 467 { 468 if (regs[APIC_INTERNAL_STATE] & 0x1) { 469 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 470 newVal = 0; 471 } else { 472 regs[APIC_INTERNAL_STATE] |= ULL(0x1); 473 return; 474 } 475 476 } 477 break; 478 case APIC_INTERRUPT_COMMAND_LOW: 479 { 480 InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 481 // Check if we're already sending an IPI. 482 if (low.deliveryStatus) { 483 newVal = low; 484 break; 485 } 486 low = val; 487 InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 488 // Record that an IPI is being sent. 489 low.deliveryStatus = 1; 490 TriggerIntMessage message; 491 message.destination = high.destination; 492 message.vector = low.vector; 493 message.deliveryMode = low.deliveryMode; 494 message.destMode = low.destMode; 495 message.level = low.level; 496 message.trigger = low.trigger; 497 bool timing = sys->getMemoryMode() == Enums::timing; 498 // Be careful no updates of the delivery status bit get lost. 499 regs[APIC_INTERRUPT_COMMAND_LOW] = low; 500 switch (low.destShorthand) { 501 case 0: 502 pendingIPIs++; 503 intPort->sendMessage(message, timing); 504 newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 505 break; 506 case 1: 507 newVal = val; 508 requestInterrupt(message.vector, 509 message.deliveryMode, message.trigger); 510 break; 511 case 2: 512 requestInterrupt(message.vector, 513 message.deliveryMode, message.trigger); 514 // Fall through 515 case 3: 516 { 517 int numContexts = sys->numContexts(); 518 pendingIPIs += (numContexts - 1); 519 for (int i = 0; i < numContexts; i++) { 520 int thisId = sys->getThreadContext(i)->contextId(); 521 if (thisId != initialApicId) { 522 PacketPtr pkt = buildIntRequest(thisId, message); 523 if (timing) 524 intPort->sendMessageTiming(pkt, latency); 525 else 526 intPort->sendMessageAtomic(pkt); 527 } 528 } 529 } 530 newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 531 break; 532 } 533 } 534 break; 535 case APIC_LVT_TIMER: 536 case APIC_LVT_THERMAL_SENSOR: 537 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 538 case APIC_LVT_LINT0: 539 case APIC_LVT_LINT1: 540 case APIC_LVT_ERROR: 541 { 542 uint64_t readOnlyMask = (1 << 12) | (1 << 14); 543 newVal = (val & ~readOnlyMask) | 544 (regs[reg] & readOnlyMask); 545 } 546 break; 547 case APIC_INITIAL_COUNT: 548 { 549 assert(clock); 550 newVal = bits(val, 31, 0); 551 // Compute how many timer ticks we're being programmed for. 552 uint64_t newCount = newVal * 553 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 554 // Schedule on the edge of the next tick plus the new count. 555 Tick offset = curTick % clock; 556 if (offset) { 557 reschedule(apicTimerEvent, 558 curTick + (newCount + 1) * clock - offset, true); 559 } else { 560 reschedule(apicTimerEvent, 561 curTick + newCount * clock, true); 562 } 563 } 564 break; 565 case APIC_CURRENT_COUNT: 566 //Local APIC Current Count register is read only. 567 return; 568 case APIC_DIVIDE_CONFIGURATION: 569 newVal = val & 0xB; 570 break; 571 default: 572 break; 573 } 574 regs[reg] = newVal; 575 return; 576} 577 578 579X86ISA::Interrupts::Interrupts(Params * p) : 580 BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0), 581 apicTimerEvent(this), 582 pendingSmi(false), smiVector(0), 583 pendingNmi(false), nmiVector(0), 584 pendingExtInt(false), extIntVector(0), 585 pendingInit(false), initVector(0), 586 pendingStartup(false), startupVector(0), 587 startedUp(false), pendingUnmaskableInt(false), 588 pendingIPIs(0), cpu(NULL) 589{ 590 pioSize = PageBytes; 591 memset(regs, 0, sizeof(regs)); 592 //Set the local apic DFR to the flat model. 593 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 594 ISRV = 0; 595 IRRV = 0; 596} 597 598 599bool 600X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 601{ 602 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 603 if (pendingUnmaskableInt) { 604 DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 605 return true; 606 } 607 if (rflags.intf) { 608 if (pendingExtInt) { 609 DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 610 return true; 611 } 612 if (IRRV > ISRV && bits(IRRV, 7, 4) > 613 bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 614 DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 615 return true; 616 } 617 } 618 return false; 619} 620 621Fault 622X86ISA::Interrupts::getInterrupt(ThreadContext *tc) 623{ 624 assert(checkInterrupts(tc)); 625 // These are all probably fairly uncommon, so we'll make them easier to 626 // check for. 627 if (pendingUnmaskableInt) { 628 if (pendingSmi) { 629 DPRINTF(LocalApic, "Generated SMI fault object.\n"); 630 return new SystemManagementInterrupt(); 631 } else if (pendingNmi) { 632 DPRINTF(LocalApic, "Generated NMI fault object.\n"); 633 return new NonMaskableInterrupt(nmiVector); 634 } else if (pendingInit) { 635 DPRINTF(LocalApic, "Generated INIT fault object.\n"); 636 return new InitInterrupt(initVector); 637 } else if (pendingStartup) { 638 DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 639 return new StartupInterrupt(startupVector); 640 } else { 641 panic("pendingUnmaskableInt set, but no unmaskable " 642 "ints were pending.\n"); 643 return NoFault; 644 } 645 } else if (pendingExtInt) { 646 DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 647 return new ExternalInterrupt(extIntVector); 648 } else { 649 DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 650 // The only thing left are fixed and lowest priority interrupts. 651 return new ExternalInterrupt(IRRV); 652 } 653} 654 655void 656X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 657{ 658 assert(checkInterrupts(tc)); 659 if (pendingUnmaskableInt) { 660 if (pendingSmi) { 661 DPRINTF(LocalApic, "SMI sent to core.\n"); 662 pendingSmi = false; 663 } else if (pendingNmi) { 664 DPRINTF(LocalApic, "NMI sent to core.\n"); 665 pendingNmi = false; 666 } else if (pendingInit) { 667 DPRINTF(LocalApic, "Init sent to core.\n"); 668 pendingInit = false; 669 startedUp = false; 670 } else if (pendingStartup) { 671 DPRINTF(LocalApic, "SIPI sent to core.\n"); 672 pendingStartup = false; 673 startedUp = true; 674 } 675 if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 676 pendingUnmaskableInt = false; 677 } else if (pendingExtInt) { 678 pendingExtInt = false; 679 } else { 680 DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 681 // Mark the interrupt as "in service". 682 ISRV = IRRV; 683 setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 684 // Clear it out of the IRR. 685 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 686 updateIRRV(); 687 } 688} 689 690X86ISA::Interrupts * 691X86LocalApicParams::create() 692{ 693 return new X86ISA::Interrupts(this); 694} 695