interrupts.cc revision 6061
15647Sgblack@eecs.umich.edu/* 25647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 35647Sgblack@eecs.umich.edu * All rights reserved. 45647Sgblack@eecs.umich.edu * 55647Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 65647Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 75647Sgblack@eecs.umich.edu * following conditions are met: 85647Sgblack@eecs.umich.edu * 95647Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 105647Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 115647Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 125647Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 135647Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 145647Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 155647Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 165647Sgblack@eecs.umich.edu * commercial advantage. 175647Sgblack@eecs.umich.edu * 185647Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 195647Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 205647Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 215647Sgblack@eecs.umich.edu * Office of Strategy and Technology 225647Sgblack@eecs.umich.edu * Hewlett-Packard Company 235647Sgblack@eecs.umich.edu * 1501 Page Mill Road 245647Sgblack@eecs.umich.edu * Palo Alto, California 94304 255647Sgblack@eecs.umich.edu * 265647Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 275647Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 285647Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 295647Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 305647Sgblack@eecs.umich.edu * other materials provided with the distribution. Neither the name of 315647Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 325647Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 335647Sgblack@eecs.umich.edu * this software without specific prior written permission. No right of 345647Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 355647Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for 365647Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 375647Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 385647Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 395647Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 405647Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 415647Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 425647Sgblack@eecs.umich.edu * 435647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 445647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 455647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 465647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 475647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 525647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545647Sgblack@eecs.umich.edu * 555647Sgblack@eecs.umich.edu * Authors: Gabe Black 565647Sgblack@eecs.umich.edu */ 575647Sgblack@eecs.umich.edu 585648Sgblack@eecs.umich.edu#include "arch/x86/apicregs.hh" 595647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 605654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 615647Sgblack@eecs.umich.edu#include "cpu/base.hh" 625654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 636046Sgblack@eecs.umich.edu#include "sim/system.hh" 645647Sgblack@eecs.umich.edu 655648Sgblack@eecs.umich.eduint 665648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 675647Sgblack@eecs.umich.edu{ 685647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 695647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 705647Sgblack@eecs.umich.edu // be deciphered fairly easily. 715647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 725647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 735647Sgblack@eecs.umich.edu return 1 << shift; 745647Sgblack@eecs.umich.edu} 755647Sgblack@eecs.umich.edu 765648Sgblack@eecs.umich.edunamespace X86ISA 775647Sgblack@eecs.umich.edu{ 785648Sgblack@eecs.umich.edu 795648Sgblack@eecs.umich.eduApicRegIndex 805648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 815648Sgblack@eecs.umich.edu{ 825648Sgblack@eecs.umich.edu ApicRegIndex regNum; 835648Sgblack@eecs.umich.edu paddr &= ~mask(3); 845648Sgblack@eecs.umich.edu switch (paddr) 855648Sgblack@eecs.umich.edu { 865648Sgblack@eecs.umich.edu case 0x20: 875648Sgblack@eecs.umich.edu regNum = APIC_ID; 885648Sgblack@eecs.umich.edu break; 895648Sgblack@eecs.umich.edu case 0x30: 905648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 915648Sgblack@eecs.umich.edu break; 925648Sgblack@eecs.umich.edu case 0x80: 935648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 945648Sgblack@eecs.umich.edu break; 955648Sgblack@eecs.umich.edu case 0x90: 965648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 975648Sgblack@eecs.umich.edu break; 985648Sgblack@eecs.umich.edu case 0xA0: 995648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 1005648Sgblack@eecs.umich.edu break; 1015648Sgblack@eecs.umich.edu case 0xB0: 1025648Sgblack@eecs.umich.edu regNum = APIC_EOI; 1035648Sgblack@eecs.umich.edu break; 1045648Sgblack@eecs.umich.edu case 0xD0: 1055648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 1065648Sgblack@eecs.umich.edu break; 1075648Sgblack@eecs.umich.edu case 0xE0: 1085648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 1095648Sgblack@eecs.umich.edu break; 1105648Sgblack@eecs.umich.edu case 0xF0: 1115648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 1125648Sgblack@eecs.umich.edu break; 1135648Sgblack@eecs.umich.edu case 0x100: 1145648Sgblack@eecs.umich.edu case 0x108: 1155648Sgblack@eecs.umich.edu case 0x110: 1165648Sgblack@eecs.umich.edu case 0x118: 1175648Sgblack@eecs.umich.edu case 0x120: 1185648Sgblack@eecs.umich.edu case 0x128: 1195648Sgblack@eecs.umich.edu case 0x130: 1205648Sgblack@eecs.umich.edu case 0x138: 1215648Sgblack@eecs.umich.edu case 0x140: 1225648Sgblack@eecs.umich.edu case 0x148: 1235648Sgblack@eecs.umich.edu case 0x150: 1245648Sgblack@eecs.umich.edu case 0x158: 1255648Sgblack@eecs.umich.edu case 0x160: 1265648Sgblack@eecs.umich.edu case 0x168: 1275648Sgblack@eecs.umich.edu case 0x170: 1285648Sgblack@eecs.umich.edu case 0x178: 1295648Sgblack@eecs.umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1305648Sgblack@eecs.umich.edu break; 1315648Sgblack@eecs.umich.edu case 0x180: 1325648Sgblack@eecs.umich.edu case 0x188: 1335648Sgblack@eecs.umich.edu case 0x190: 1345648Sgblack@eecs.umich.edu case 0x198: 1355648Sgblack@eecs.umich.edu case 0x1A0: 1365648Sgblack@eecs.umich.edu case 0x1A8: 1375648Sgblack@eecs.umich.edu case 0x1B0: 1385648Sgblack@eecs.umich.edu case 0x1B8: 1395648Sgblack@eecs.umich.edu case 0x1C0: 1405648Sgblack@eecs.umich.edu case 0x1C8: 1415648Sgblack@eecs.umich.edu case 0x1D0: 1425648Sgblack@eecs.umich.edu case 0x1D8: 1435648Sgblack@eecs.umich.edu case 0x1E0: 1445648Sgblack@eecs.umich.edu case 0x1E8: 1455648Sgblack@eecs.umich.edu case 0x1F0: 1465648Sgblack@eecs.umich.edu case 0x1F8: 1475648Sgblack@eecs.umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1485648Sgblack@eecs.umich.edu break; 1495648Sgblack@eecs.umich.edu case 0x200: 1505648Sgblack@eecs.umich.edu case 0x208: 1515648Sgblack@eecs.umich.edu case 0x210: 1525648Sgblack@eecs.umich.edu case 0x218: 1535648Sgblack@eecs.umich.edu case 0x220: 1545648Sgblack@eecs.umich.edu case 0x228: 1555648Sgblack@eecs.umich.edu case 0x230: 1565648Sgblack@eecs.umich.edu case 0x238: 1575648Sgblack@eecs.umich.edu case 0x240: 1585648Sgblack@eecs.umich.edu case 0x248: 1595648Sgblack@eecs.umich.edu case 0x250: 1605648Sgblack@eecs.umich.edu case 0x258: 1615648Sgblack@eecs.umich.edu case 0x260: 1625648Sgblack@eecs.umich.edu case 0x268: 1635648Sgblack@eecs.umich.edu case 0x270: 1645648Sgblack@eecs.umich.edu case 0x278: 1655648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1665648Sgblack@eecs.umich.edu break; 1675648Sgblack@eecs.umich.edu case 0x280: 1685648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1695648Sgblack@eecs.umich.edu break; 1705648Sgblack@eecs.umich.edu case 0x300: 1715648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1725648Sgblack@eecs.umich.edu break; 1735648Sgblack@eecs.umich.edu case 0x310: 1745648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1755648Sgblack@eecs.umich.edu break; 1765648Sgblack@eecs.umich.edu case 0x320: 1775648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1785648Sgblack@eecs.umich.edu break; 1795648Sgblack@eecs.umich.edu case 0x330: 1805648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1815648Sgblack@eecs.umich.edu break; 1825648Sgblack@eecs.umich.edu case 0x340: 1835648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1845648Sgblack@eecs.umich.edu break; 1855648Sgblack@eecs.umich.edu case 0x350: 1865648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1875648Sgblack@eecs.umich.edu break; 1885648Sgblack@eecs.umich.edu case 0x360: 1895648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1905648Sgblack@eecs.umich.edu break; 1915648Sgblack@eecs.umich.edu case 0x370: 1925648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1935648Sgblack@eecs.umich.edu break; 1945648Sgblack@eecs.umich.edu case 0x380: 1955648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1965648Sgblack@eecs.umich.edu break; 1975648Sgblack@eecs.umich.edu case 0x390: 1985648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1995648Sgblack@eecs.umich.edu break; 2005648Sgblack@eecs.umich.edu case 0x3E0: 2015648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 2025648Sgblack@eecs.umich.edu break; 2035648Sgblack@eecs.umich.edu default: 2045648Sgblack@eecs.umich.edu // A reserved register field. 2055648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 2065648Sgblack@eecs.umich.edu break; 2075648Sgblack@eecs.umich.edu } 2085648Sgblack@eecs.umich.edu return regNum; 2095648Sgblack@eecs.umich.edu} 2105648Sgblack@eecs.umich.edu} 2115648Sgblack@eecs.umich.edu 2125648Sgblack@eecs.umich.eduTick 2135648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 2145648Sgblack@eecs.umich.edu{ 2155648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2165648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2175648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2185648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2195648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2205648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 2215649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2225649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2235649Sgblack@eecs.umich.edu reg, offset, val); 2245648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2255898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2265648Sgblack@eecs.umich.edu return latency; 2275648Sgblack@eecs.umich.edu} 2285648Sgblack@eecs.umich.edu 2295648Sgblack@eecs.umich.eduTick 2305648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2315648Sgblack@eecs.umich.edu{ 2325648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2335648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2345648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2355648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2365648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2375648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2385648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2395649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2405649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2415649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2425648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2435898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2445648Sgblack@eecs.umich.edu return latency; 2455647Sgblack@eecs.umich.edu} 2465691Sgblack@eecs.umich.eduvoid 2475691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2485691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2495691Sgblack@eecs.umich.edu{ 2505691Sgblack@eecs.umich.edu /* 2515691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2525691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2535691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2545691Sgblack@eecs.umich.edu */ 2555691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2565691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2575691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2585691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2595691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2605691Sgblack@eecs.umich.edu if (vector > IRRV) 2615691Sgblack@eecs.umich.edu IRRV = vector; 2625691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2635691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2645691Sgblack@eecs.umich.edu if (level) { 2655691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2665691Sgblack@eecs.umich.edu } else { 2675691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2685691Sgblack@eecs.umich.edu } 2695691Sgblack@eecs.umich.edu } 2705691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2715691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2725691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2735691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2745691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2755691Sgblack@eecs.umich.edu smiVector = vector; 2765691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2775691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2785691Sgblack@eecs.umich.edu nmiVector = vector; 2795691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2805691Sgblack@eecs.umich.edu pendingExtInt = true; 2815691Sgblack@eecs.umich.edu extIntVector = vector; 2825691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2835691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2845691Sgblack@eecs.umich.edu initVector = vector; 2856050Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && !pendingStartup) { 2866050Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2876050Sgblack@eecs.umich.edu startupVector = vector; 2885691Sgblack@eecs.umich.edu } 2895691Sgblack@eecs.umich.edu } 2905811Sgblack@eecs.umich.edu cpu->wakeup(); 2915691Sgblack@eecs.umich.edu} 2925647Sgblack@eecs.umich.edu 2936041Sgblack@eecs.umich.edu 2946041Sgblack@eecs.umich.eduvoid 2956041Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2966041Sgblack@eecs.umich.edu{ 2976041Sgblack@eecs.umich.edu cpu = newCPU; 2986041Sgblack@eecs.umich.edu assert(cpu); 2996041Sgblack@eecs.umich.edu regs[APIC_ID] = (cpu->cpuId() << 24); 3006041Sgblack@eecs.umich.edu} 3016041Sgblack@eecs.umich.edu 3026041Sgblack@eecs.umich.edu 3035651Sgblack@eecs.umich.eduTick 3045651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3055651Sgblack@eecs.umich.edu{ 3066041Sgblack@eecs.umich.edu uint8_t id = (regs[APIC_ID] >> 24); 3075654Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0); 3085651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3095651Sgblack@eecs.umich.edu switch(offset) 3105651Sgblack@eecs.umich.edu { 3115651Sgblack@eecs.umich.edu case 0: 3125654Sgblack@eecs.umich.edu { 3135654Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3145654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3155654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3165697Snate@binkert.org message.vector); 3175654Sgblack@eecs.umich.edu // Make sure we're really supposed to get this. 3185654Sgblack@eecs.umich.edu assert((message.destMode == 0 && message.destination == id) || 3195654Sgblack@eecs.umich.edu (bits((int)message.destination, id))); 3205655Sgblack@eecs.umich.edu 3215691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3225691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3235654Sgblack@eecs.umich.edu } 3245651Sgblack@eecs.umich.edu break; 3255651Sgblack@eecs.umich.edu default: 3265651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3275651Sgblack@eecs.umich.edu offset); 3285651Sgblack@eecs.umich.edu break; 3295651Sgblack@eecs.umich.edu } 3305651Sgblack@eecs.umich.edu delete pkt->req; 3315651Sgblack@eecs.umich.edu delete pkt; 3325651Sgblack@eecs.umich.edu return latency; 3335651Sgblack@eecs.umich.edu} 3345651Sgblack@eecs.umich.edu 3355651Sgblack@eecs.umich.edu 3366041Sgblack@eecs.umich.eduvoid 3376041Sgblack@eecs.umich.eduX86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 3386041Sgblack@eecs.umich.edu{ 3396041Sgblack@eecs.umich.edu uint8_t id = (regs[APIC_ID] >> 24); 3406041Sgblack@eecs.umich.edu range_list.clear(); 3416061Sgblack@eecs.umich.edu Range<Addr> range = RangeEx(x86LocalAPICAddress(id, 0), 3426061Sgblack@eecs.umich.edu x86LocalAPICAddress(id, 0) + PageBytes); 3436061Sgblack@eecs.umich.edu range_list.push_back(range); 3446061Sgblack@eecs.umich.edu pioAddr = range.start; 3456041Sgblack@eecs.umich.edu} 3466041Sgblack@eecs.umich.edu 3476041Sgblack@eecs.umich.edu 3486041Sgblack@eecs.umich.eduvoid 3496041Sgblack@eecs.umich.eduX86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 3506041Sgblack@eecs.umich.edu{ 3516041Sgblack@eecs.umich.edu uint8_t id = (regs[APIC_ID] >> 24); 3526041Sgblack@eecs.umich.edu range_list.clear(); 3536041Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86InterruptAddress(id, 0), 3546041Sgblack@eecs.umich.edu x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize)); 3556041Sgblack@eecs.umich.edu} 3566041Sgblack@eecs.umich.edu 3576041Sgblack@eecs.umich.edu 3585647Sgblack@eecs.umich.eduuint32_t 3595648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3605647Sgblack@eecs.umich.edu{ 3615647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3625647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3635647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3645647Sgblack@eecs.umich.edu } 3655647Sgblack@eecs.umich.edu switch (reg) { 3665647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3675647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3685647Sgblack@eecs.umich.edu break; 3695647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 3705647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 3715647Sgblack@eecs.umich.edu break; 3725647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 3735647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 3745647Sgblack@eecs.umich.edu break; 3755647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 3765647Sgblack@eecs.umich.edu { 3775848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 3785848Sgblack@eecs.umich.edu assert(clock); 3795848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 3805848Sgblack@eecs.umich.edu uint64_t ticksPerCount = clock * 3815848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 3825848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 3835848Sgblack@eecs.umich.edu uint64_t val = apicTimerEvent.when() - curTick; 3845848Sgblack@eecs.umich.edu // Turn that into a count. 3855848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 3865848Sgblack@eecs.umich.edu return val; 3875848Sgblack@eecs.umich.edu } else { 3885848Sgblack@eecs.umich.edu return 0; 3895848Sgblack@eecs.umich.edu } 3905647Sgblack@eecs.umich.edu } 3915647Sgblack@eecs.umich.edu default: 3925647Sgblack@eecs.umich.edu break; 3935647Sgblack@eecs.umich.edu } 3945648Sgblack@eecs.umich.edu return regs[reg]; 3955647Sgblack@eecs.umich.edu} 3965647Sgblack@eecs.umich.edu 3975647Sgblack@eecs.umich.eduvoid 3985648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 3995647Sgblack@eecs.umich.edu{ 4005647Sgblack@eecs.umich.edu uint32_t newVal = val; 4015647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4025647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4035647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4045647Sgblack@eecs.umich.edu } 4055647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4065647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4075647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4085647Sgblack@eecs.umich.edu } 4095647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4105647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4115647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4125647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4135647Sgblack@eecs.umich.edu } 4145647Sgblack@eecs.umich.edu switch (reg) { 4155647Sgblack@eecs.umich.edu case APIC_ID: 4165647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4175647Sgblack@eecs.umich.edu break; 4185647Sgblack@eecs.umich.edu case APIC_VERSION: 4195647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4205647Sgblack@eecs.umich.edu return; 4215647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4225647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4235647Sgblack@eecs.umich.edu break; 4245647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4255647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4265647Sgblack@eecs.umich.edu break; 4275647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4285647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4295647Sgblack@eecs.umich.edu break; 4305647Sgblack@eecs.umich.edu case APIC_EOI: 4315690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4325690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4335690Sgblack@eecs.umich.edu updateISRV(); 4345690Sgblack@eecs.umich.edu return; 4355647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4365647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4375647Sgblack@eecs.umich.edu break; 4385647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4395647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4405647Sgblack@eecs.umich.edu break; 4415647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4425647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4435647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4445647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4455647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4465647Sgblack@eecs.umich.edu break; 4475647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4485647Sgblack@eecs.umich.edu { 4495647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4505647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4515647Sgblack@eecs.umich.edu newVal = 0; 4525647Sgblack@eecs.umich.edu } else { 4535647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4545647Sgblack@eecs.umich.edu return; 4555647Sgblack@eecs.umich.edu } 4565647Sgblack@eecs.umich.edu 4575647Sgblack@eecs.umich.edu } 4585647Sgblack@eecs.umich.edu break; 4595647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4606046Sgblack@eecs.umich.edu { 4616046Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 4626046Sgblack@eecs.umich.edu // Check if we're already sending an IPI. 4636046Sgblack@eecs.umich.edu if (low.deliveryStatus) { 4646046Sgblack@eecs.umich.edu newVal = low; 4656046Sgblack@eecs.umich.edu break; 4666046Sgblack@eecs.umich.edu } 4676046Sgblack@eecs.umich.edu low = val; 4686046Sgblack@eecs.umich.edu InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 4696046Sgblack@eecs.umich.edu // Record that an IPI is being sent. 4706046Sgblack@eecs.umich.edu low.deliveryStatus = 1; 4716046Sgblack@eecs.umich.edu TriggerIntMessage message; 4726046Sgblack@eecs.umich.edu message.destination = high.destination; 4736046Sgblack@eecs.umich.edu message.vector = low.vector; 4746046Sgblack@eecs.umich.edu message.deliveryMode = low.deliveryMode; 4756046Sgblack@eecs.umich.edu message.destMode = low.destMode; 4766046Sgblack@eecs.umich.edu message.level = low.level; 4776046Sgblack@eecs.umich.edu message.trigger = low.trigger; 4786046Sgblack@eecs.umich.edu bool timing = sys->getMemoryMode() == Enums::timing; 4796046Sgblack@eecs.umich.edu switch (low.destShorthand) { 4806046Sgblack@eecs.umich.edu case 0: 4816046Sgblack@eecs.umich.edu intPort->sendMessage(message, timing); 4826046Sgblack@eecs.umich.edu break; 4836046Sgblack@eecs.umich.edu case 1: 4846046Sgblack@eecs.umich.edu panic("Self IPIs aren't implemented.\n"); 4856046Sgblack@eecs.umich.edu break; 4866046Sgblack@eecs.umich.edu case 2: 4876046Sgblack@eecs.umich.edu panic("Broadcast including self IPIs aren't implemented.\n"); 4886046Sgblack@eecs.umich.edu break; 4896046Sgblack@eecs.umich.edu case 3: 4906046Sgblack@eecs.umich.edu panic("Broadcast excluding self IPIs aren't implemented.\n"); 4916046Sgblack@eecs.umich.edu break; 4926046Sgblack@eecs.umich.edu } 4936046Sgblack@eecs.umich.edu } 4945647Sgblack@eecs.umich.edu break; 4955647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 4965647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 4975647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 4985647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 4995647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 5005647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 5015647Sgblack@eecs.umich.edu { 5025647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 5035647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 5045647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 5055647Sgblack@eecs.umich.edu } 5065647Sgblack@eecs.umich.edu break; 5075647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 5085648Sgblack@eecs.umich.edu { 5095648Sgblack@eecs.umich.edu assert(clock); 5105648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 5115848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 5125848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 5135848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 5145648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 5155848Sgblack@eecs.umich.edu Tick offset = curTick % clock; 5165648Sgblack@eecs.umich.edu if (offset) { 5175648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5185848Sgblack@eecs.umich.edu curTick + (newCount + 1) * clock - offset, true); 5195648Sgblack@eecs.umich.edu } else { 5205648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5215848Sgblack@eecs.umich.edu curTick + newCount * clock, true); 5225648Sgblack@eecs.umich.edu } 5235648Sgblack@eecs.umich.edu } 5245647Sgblack@eecs.umich.edu break; 5255647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 5265647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 5275647Sgblack@eecs.umich.edu return; 5285647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 5295647Sgblack@eecs.umich.edu newVal = val & 0xB; 5305647Sgblack@eecs.umich.edu break; 5315647Sgblack@eecs.umich.edu default: 5325647Sgblack@eecs.umich.edu break; 5335647Sgblack@eecs.umich.edu } 5345648Sgblack@eecs.umich.edu regs[reg] = newVal; 5355647Sgblack@eecs.umich.edu return; 5365647Sgblack@eecs.umich.edu} 5375647Sgblack@eecs.umich.edu 5386041Sgblack@eecs.umich.edu 5396041Sgblack@eecs.umich.eduX86ISA::Interrupts::Interrupts(Params * p) : 5406041Sgblack@eecs.umich.edu BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0), 5416041Sgblack@eecs.umich.edu apicTimerEvent(this), 5426041Sgblack@eecs.umich.edu pendingSmi(false), smiVector(0), 5436041Sgblack@eecs.umich.edu pendingNmi(false), nmiVector(0), 5446041Sgblack@eecs.umich.edu pendingExtInt(false), extIntVector(0), 5456041Sgblack@eecs.umich.edu pendingInit(false), initVector(0), 5466050Sgblack@eecs.umich.edu pendingStartup(false), startupVector(0), 5476041Sgblack@eecs.umich.edu pendingUnmaskableInt(false) 5486041Sgblack@eecs.umich.edu{ 5496041Sgblack@eecs.umich.edu pioSize = PageBytes; 5506041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 5516041Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 5526041Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 5536041Sgblack@eecs.umich.edu ISRV = 0; 5546041Sgblack@eecs.umich.edu IRRV = 0; 5556041Sgblack@eecs.umich.edu} 5566041Sgblack@eecs.umich.edu 5576041Sgblack@eecs.umich.edu 5585654Sgblack@eecs.umich.edubool 5595704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 5605654Sgblack@eecs.umich.edu{ 5615654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 5625689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 5635689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 5645654Sgblack@eecs.umich.edu return true; 5655689Sgblack@eecs.umich.edu } 5665655Sgblack@eecs.umich.edu if (rflags.intf) { 5675689Sgblack@eecs.umich.edu if (pendingExtInt) { 5685689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 5695655Sgblack@eecs.umich.edu return true; 5705689Sgblack@eecs.umich.edu } 5715655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 5725689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 5735689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 5745655Sgblack@eecs.umich.edu return true; 5755689Sgblack@eecs.umich.edu } 5765654Sgblack@eecs.umich.edu } 5775654Sgblack@eecs.umich.edu return false; 5785654Sgblack@eecs.umich.edu} 5795654Sgblack@eecs.umich.edu 5805654Sgblack@eecs.umich.eduFault 5815704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 5825654Sgblack@eecs.umich.edu{ 5835704Snate@binkert.org assert(checkInterrupts(tc)); 5845655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 5855655Sgblack@eecs.umich.edu // check for. 5865655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 5875655Sgblack@eecs.umich.edu if (pendingSmi) { 5885689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 5895655Sgblack@eecs.umich.edu return new SystemManagementInterrupt(); 5905655Sgblack@eecs.umich.edu } else if (pendingNmi) { 5915689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 5925691Sgblack@eecs.umich.edu return new NonMaskableInterrupt(nmiVector); 5935655Sgblack@eecs.umich.edu } else if (pendingInit) { 5945689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 5955691Sgblack@eecs.umich.edu return new InitInterrupt(initVector); 5966050Sgblack@eecs.umich.edu } else if (pendingStartup) { 5976050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 5986050Sgblack@eecs.umich.edu return new StartupInterrupt(startupVector); 5995655Sgblack@eecs.umich.edu } else { 6005655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 6015655Sgblack@eecs.umich.edu "ints were pending.\n"); 6025655Sgblack@eecs.umich.edu return NoFault; 6035655Sgblack@eecs.umich.edu } 6045655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6055689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 6065691Sgblack@eecs.umich.edu return new ExternalInterrupt(extIntVector); 6075655Sgblack@eecs.umich.edu } else { 6085689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 6095655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 6105655Sgblack@eecs.umich.edu return new ExternalInterrupt(IRRV); 6115655Sgblack@eecs.umich.edu } 6125654Sgblack@eecs.umich.edu} 6135654Sgblack@eecs.umich.edu 6145654Sgblack@eecs.umich.eduvoid 6155704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 6165654Sgblack@eecs.umich.edu{ 6175704Snate@binkert.org assert(checkInterrupts(tc)); 6185655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6195655Sgblack@eecs.umich.edu if (pendingSmi) { 6205689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 6215655Sgblack@eecs.umich.edu pendingSmi = false; 6225655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6235689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 6245655Sgblack@eecs.umich.edu pendingNmi = false; 6255655Sgblack@eecs.umich.edu } else if (pendingInit) { 6265689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 6275655Sgblack@eecs.umich.edu pendingInit = false; 6286050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6296050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SIPI sent to core.\n"); 6306050Sgblack@eecs.umich.edu pendingStartup = false; 6315655Sgblack@eecs.umich.edu } 6326050Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 6335655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 6345655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6355655Sgblack@eecs.umich.edu pendingExtInt = false; 6365655Sgblack@eecs.umich.edu } else { 6375689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 6385655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 6395655Sgblack@eecs.umich.edu ISRV = IRRV; 6405655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 6415655Sgblack@eecs.umich.edu // Clear it out of the IRR. 6425655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 6435655Sgblack@eecs.umich.edu updateIRRV(); 6445655Sgblack@eecs.umich.edu } 6455654Sgblack@eecs.umich.edu} 6465654Sgblack@eecs.umich.edu 6475647Sgblack@eecs.umich.eduX86ISA::Interrupts * 6485647Sgblack@eecs.umich.eduX86LocalApicParams::create() 6495647Sgblack@eecs.umich.edu{ 6505647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 6515647Sgblack@eecs.umich.edu} 652