interrupts.cc revision 6041
15647Sgblack@eecs.umich.edu/* 25647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 35647Sgblack@eecs.umich.edu * All rights reserved. 45647Sgblack@eecs.umich.edu * 55647Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 65647Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 75647Sgblack@eecs.umich.edu * following conditions are met: 85647Sgblack@eecs.umich.edu * 95647Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 105647Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 115647Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. 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Derivatives of the software may be shared with 375647Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 385647Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 395647Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 405647Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 415647Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 425647Sgblack@eecs.umich.edu * 435647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 445647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 455647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 465647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 475647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 525647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545647Sgblack@eecs.umich.edu * 555647Sgblack@eecs.umich.edu * Authors: Gabe Black 565647Sgblack@eecs.umich.edu */ 575647Sgblack@eecs.umich.edu 585648Sgblack@eecs.umich.edu#include "arch/x86/apicregs.hh" 595647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 605654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 615647Sgblack@eecs.umich.edu#include "cpu/base.hh" 625654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 635647Sgblack@eecs.umich.edu 645648Sgblack@eecs.umich.eduint 655648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 665647Sgblack@eecs.umich.edu{ 675647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 685647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 695647Sgblack@eecs.umich.edu // be deciphered fairly easily. 705647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 715647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 725647Sgblack@eecs.umich.edu return 1 << shift; 735647Sgblack@eecs.umich.edu} 745647Sgblack@eecs.umich.edu 755648Sgblack@eecs.umich.edunamespace X86ISA 765647Sgblack@eecs.umich.edu{ 775648Sgblack@eecs.umich.edu 785648Sgblack@eecs.umich.eduApicRegIndex 795648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 805648Sgblack@eecs.umich.edu{ 815648Sgblack@eecs.umich.edu ApicRegIndex regNum; 825648Sgblack@eecs.umich.edu paddr &= ~mask(3); 835648Sgblack@eecs.umich.edu switch (paddr) 845648Sgblack@eecs.umich.edu { 855648Sgblack@eecs.umich.edu case 0x20: 865648Sgblack@eecs.umich.edu regNum = APIC_ID; 875648Sgblack@eecs.umich.edu break; 885648Sgblack@eecs.umich.edu case 0x30: 895648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 905648Sgblack@eecs.umich.edu break; 915648Sgblack@eecs.umich.edu case 0x80: 925648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 935648Sgblack@eecs.umich.edu break; 945648Sgblack@eecs.umich.edu case 0x90: 955648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 965648Sgblack@eecs.umich.edu break; 975648Sgblack@eecs.umich.edu case 0xA0: 985648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 995648Sgblack@eecs.umich.edu break; 1005648Sgblack@eecs.umich.edu case 0xB0: 1015648Sgblack@eecs.umich.edu regNum = APIC_EOI; 1025648Sgblack@eecs.umich.edu break; 1035648Sgblack@eecs.umich.edu case 0xD0: 1045648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 1055648Sgblack@eecs.umich.edu break; 1065648Sgblack@eecs.umich.edu case 0xE0: 1075648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 1085648Sgblack@eecs.umich.edu break; 1095648Sgblack@eecs.umich.edu case 0xF0: 1105648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 1115648Sgblack@eecs.umich.edu break; 1125648Sgblack@eecs.umich.edu case 0x100: 1135648Sgblack@eecs.umich.edu case 0x108: 1145648Sgblack@eecs.umich.edu case 0x110: 1155648Sgblack@eecs.umich.edu case 0x118: 1165648Sgblack@eecs.umich.edu case 0x120: 1175648Sgblack@eecs.umich.edu case 0x128: 1185648Sgblack@eecs.umich.edu case 0x130: 1195648Sgblack@eecs.umich.edu case 0x138: 1205648Sgblack@eecs.umich.edu case 0x140: 1215648Sgblack@eecs.umich.edu case 0x148: 1225648Sgblack@eecs.umich.edu case 0x150: 1235648Sgblack@eecs.umich.edu case 0x158: 1245648Sgblack@eecs.umich.edu case 0x160: 1255648Sgblack@eecs.umich.edu case 0x168: 1265648Sgblack@eecs.umich.edu case 0x170: 1275648Sgblack@eecs.umich.edu case 0x178: 1285648Sgblack@eecs.umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1295648Sgblack@eecs.umich.edu break; 1305648Sgblack@eecs.umich.edu case 0x180: 1315648Sgblack@eecs.umich.edu case 0x188: 1325648Sgblack@eecs.umich.edu case 0x190: 1335648Sgblack@eecs.umich.edu case 0x198: 1345648Sgblack@eecs.umich.edu case 0x1A0: 1355648Sgblack@eecs.umich.edu case 0x1A8: 1365648Sgblack@eecs.umich.edu case 0x1B0: 1375648Sgblack@eecs.umich.edu case 0x1B8: 1385648Sgblack@eecs.umich.edu case 0x1C0: 1395648Sgblack@eecs.umich.edu case 0x1C8: 1405648Sgblack@eecs.umich.edu case 0x1D0: 1415648Sgblack@eecs.umich.edu case 0x1D8: 1425648Sgblack@eecs.umich.edu case 0x1E0: 1435648Sgblack@eecs.umich.edu case 0x1E8: 1445648Sgblack@eecs.umich.edu case 0x1F0: 1455648Sgblack@eecs.umich.edu case 0x1F8: 1465648Sgblack@eecs.umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1475648Sgblack@eecs.umich.edu break; 1485648Sgblack@eecs.umich.edu case 0x200: 1495648Sgblack@eecs.umich.edu case 0x208: 1505648Sgblack@eecs.umich.edu case 0x210: 1515648Sgblack@eecs.umich.edu case 0x218: 1525648Sgblack@eecs.umich.edu case 0x220: 1535648Sgblack@eecs.umich.edu case 0x228: 1545648Sgblack@eecs.umich.edu case 0x230: 1555648Sgblack@eecs.umich.edu case 0x238: 1565648Sgblack@eecs.umich.edu case 0x240: 1575648Sgblack@eecs.umich.edu case 0x248: 1585648Sgblack@eecs.umich.edu case 0x250: 1595648Sgblack@eecs.umich.edu case 0x258: 1605648Sgblack@eecs.umich.edu case 0x260: 1615648Sgblack@eecs.umich.edu case 0x268: 1625648Sgblack@eecs.umich.edu case 0x270: 1635648Sgblack@eecs.umich.edu case 0x278: 1645648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1655648Sgblack@eecs.umich.edu break; 1665648Sgblack@eecs.umich.edu case 0x280: 1675648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1685648Sgblack@eecs.umich.edu break; 1695648Sgblack@eecs.umich.edu case 0x300: 1705648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1715648Sgblack@eecs.umich.edu break; 1725648Sgblack@eecs.umich.edu case 0x310: 1735648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1745648Sgblack@eecs.umich.edu break; 1755648Sgblack@eecs.umich.edu case 0x320: 1765648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1775648Sgblack@eecs.umich.edu break; 1785648Sgblack@eecs.umich.edu case 0x330: 1795648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1805648Sgblack@eecs.umich.edu break; 1815648Sgblack@eecs.umich.edu case 0x340: 1825648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1835648Sgblack@eecs.umich.edu break; 1845648Sgblack@eecs.umich.edu case 0x350: 1855648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1865648Sgblack@eecs.umich.edu break; 1875648Sgblack@eecs.umich.edu case 0x360: 1885648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1895648Sgblack@eecs.umich.edu break; 1905648Sgblack@eecs.umich.edu case 0x370: 1915648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1925648Sgblack@eecs.umich.edu break; 1935648Sgblack@eecs.umich.edu case 0x380: 1945648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1955648Sgblack@eecs.umich.edu break; 1965648Sgblack@eecs.umich.edu case 0x390: 1975648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1985648Sgblack@eecs.umich.edu break; 1995648Sgblack@eecs.umich.edu case 0x3E0: 2005648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 2015648Sgblack@eecs.umich.edu break; 2025648Sgblack@eecs.umich.edu default: 2035648Sgblack@eecs.umich.edu // A reserved register field. 2045648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 2055648Sgblack@eecs.umich.edu break; 2065648Sgblack@eecs.umich.edu } 2075648Sgblack@eecs.umich.edu return regNum; 2085648Sgblack@eecs.umich.edu} 2095648Sgblack@eecs.umich.edu} 2105648Sgblack@eecs.umich.edu 2115648Sgblack@eecs.umich.eduTick 2125648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 2135648Sgblack@eecs.umich.edu{ 2145648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2155648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2165648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2175648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2185648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2195648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 2205649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2215649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2225649Sgblack@eecs.umich.edu reg, offset, val); 2235648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2245898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2255648Sgblack@eecs.umich.edu return latency; 2265648Sgblack@eecs.umich.edu} 2275648Sgblack@eecs.umich.edu 2285648Sgblack@eecs.umich.eduTick 2295648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2305648Sgblack@eecs.umich.edu{ 2315648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2325648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2335648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2345648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2355648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2365648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2375648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2385649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2395649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2405649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2415648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2425898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2435648Sgblack@eecs.umich.edu return latency; 2445647Sgblack@eecs.umich.edu} 2455691Sgblack@eecs.umich.eduvoid 2465691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2475691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2485691Sgblack@eecs.umich.edu{ 2495691Sgblack@eecs.umich.edu /* 2505691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2515691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2525691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2535691Sgblack@eecs.umich.edu */ 2545691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2555691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2565691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2575691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2585691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2595691Sgblack@eecs.umich.edu if (vector > IRRV) 2605691Sgblack@eecs.umich.edu IRRV = vector; 2615691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2625691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2635691Sgblack@eecs.umich.edu if (level) { 2645691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2655691Sgblack@eecs.umich.edu } else { 2665691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2675691Sgblack@eecs.umich.edu } 2685691Sgblack@eecs.umich.edu } 2695691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2705691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2715691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2725691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2735691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2745691Sgblack@eecs.umich.edu smiVector = vector; 2755691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2765691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2775691Sgblack@eecs.umich.edu nmiVector = vector; 2785691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2795691Sgblack@eecs.umich.edu pendingExtInt = true; 2805691Sgblack@eecs.umich.edu extIntVector = vector; 2815691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2825691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2835691Sgblack@eecs.umich.edu initVector = vector; 2845691Sgblack@eecs.umich.edu } 2855691Sgblack@eecs.umich.edu } 2865811Sgblack@eecs.umich.edu cpu->wakeup(); 2875691Sgblack@eecs.umich.edu} 2885647Sgblack@eecs.umich.edu 2896041Sgblack@eecs.umich.edu 2906041Sgblack@eecs.umich.eduvoid 2916041Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2926041Sgblack@eecs.umich.edu{ 2936041Sgblack@eecs.umich.edu cpu = newCPU; 2946041Sgblack@eecs.umich.edu assert(cpu); 2956041Sgblack@eecs.umich.edu regs[APIC_ID] = (cpu->cpuId() << 24); 2966041Sgblack@eecs.umich.edu} 2976041Sgblack@eecs.umich.edu 2986041Sgblack@eecs.umich.edu 2995651Sgblack@eecs.umich.eduTick 3005651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3015651Sgblack@eecs.umich.edu{ 3026041Sgblack@eecs.umich.edu uint8_t id = (regs[APIC_ID] >> 24); 3035654Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0); 3045651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3055651Sgblack@eecs.umich.edu switch(offset) 3065651Sgblack@eecs.umich.edu { 3075651Sgblack@eecs.umich.edu case 0: 3085654Sgblack@eecs.umich.edu { 3095654Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3105654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3115654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3125697Snate@binkert.org message.vector); 3135654Sgblack@eecs.umich.edu // Make sure we're really supposed to get this. 3145654Sgblack@eecs.umich.edu assert((message.destMode == 0 && message.destination == id) || 3155654Sgblack@eecs.umich.edu (bits((int)message.destination, id))); 3165655Sgblack@eecs.umich.edu 3175691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3185691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3195654Sgblack@eecs.umich.edu } 3205651Sgblack@eecs.umich.edu break; 3215651Sgblack@eecs.umich.edu default: 3225651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3235651Sgblack@eecs.umich.edu offset); 3245651Sgblack@eecs.umich.edu break; 3255651Sgblack@eecs.umich.edu } 3265651Sgblack@eecs.umich.edu delete pkt->req; 3275651Sgblack@eecs.umich.edu delete pkt; 3285651Sgblack@eecs.umich.edu return latency; 3295651Sgblack@eecs.umich.edu} 3305651Sgblack@eecs.umich.edu 3315651Sgblack@eecs.umich.edu 3326041Sgblack@eecs.umich.eduvoid 3336041Sgblack@eecs.umich.eduX86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 3346041Sgblack@eecs.umich.edu{ 3356041Sgblack@eecs.umich.edu uint8_t id = (regs[APIC_ID] >> 24); 3366041Sgblack@eecs.umich.edu range_list.clear(); 3376041Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86LocalAPICAddress(id, 0), 3386041Sgblack@eecs.umich.edu x86LocalAPICAddress(id, 0) + PageBytes)); 3396041Sgblack@eecs.umich.edu} 3406041Sgblack@eecs.umich.edu 3416041Sgblack@eecs.umich.edu 3426041Sgblack@eecs.umich.eduvoid 3436041Sgblack@eecs.umich.eduX86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 3446041Sgblack@eecs.umich.edu{ 3456041Sgblack@eecs.umich.edu uint8_t id = (regs[APIC_ID] >> 24); 3466041Sgblack@eecs.umich.edu range_list.clear(); 3476041Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86InterruptAddress(id, 0), 3486041Sgblack@eecs.umich.edu x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize)); 3496041Sgblack@eecs.umich.edu} 3506041Sgblack@eecs.umich.edu 3516041Sgblack@eecs.umich.edu 3525647Sgblack@eecs.umich.eduuint32_t 3535648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3545647Sgblack@eecs.umich.edu{ 3555647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3565647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3575647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3585647Sgblack@eecs.umich.edu } 3595647Sgblack@eecs.umich.edu switch (reg) { 3605647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3615647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3625647Sgblack@eecs.umich.edu break; 3635647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 3645647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 3655647Sgblack@eecs.umich.edu break; 3665647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 3675647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 3685647Sgblack@eecs.umich.edu break; 3695647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 3705647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Command low" 3715647Sgblack@eecs.umich.edu " register unimplemented.\n"); 3725647Sgblack@eecs.umich.edu break; 3735647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_HIGH: 3745647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Command high" 3755647Sgblack@eecs.umich.edu " register unimplemented.\n"); 3765647Sgblack@eecs.umich.edu break; 3775647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 3785647Sgblack@eecs.umich.edu { 3795848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 3805848Sgblack@eecs.umich.edu assert(clock); 3815848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 3825848Sgblack@eecs.umich.edu uint64_t ticksPerCount = clock * 3835848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 3845848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 3855848Sgblack@eecs.umich.edu uint64_t val = apicTimerEvent.when() - curTick; 3865848Sgblack@eecs.umich.edu // Turn that into a count. 3875848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 3885848Sgblack@eecs.umich.edu return val; 3895848Sgblack@eecs.umich.edu } else { 3905848Sgblack@eecs.umich.edu return 0; 3915848Sgblack@eecs.umich.edu } 3925647Sgblack@eecs.umich.edu } 3935647Sgblack@eecs.umich.edu default: 3945647Sgblack@eecs.umich.edu break; 3955647Sgblack@eecs.umich.edu } 3965648Sgblack@eecs.umich.edu return regs[reg]; 3975647Sgblack@eecs.umich.edu} 3985647Sgblack@eecs.umich.edu 3995647Sgblack@eecs.umich.eduvoid 4005648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 4015647Sgblack@eecs.umich.edu{ 4025647Sgblack@eecs.umich.edu uint32_t newVal = val; 4035647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4045647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4055647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4065647Sgblack@eecs.umich.edu } 4075647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4085647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4095647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4105647Sgblack@eecs.umich.edu } 4115647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4125647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4135647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4145647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4155647Sgblack@eecs.umich.edu } 4165647Sgblack@eecs.umich.edu switch (reg) { 4175647Sgblack@eecs.umich.edu case APIC_ID: 4185647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4195647Sgblack@eecs.umich.edu break; 4205647Sgblack@eecs.umich.edu case APIC_VERSION: 4215647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4225647Sgblack@eecs.umich.edu return; 4235647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4245647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4255647Sgblack@eecs.umich.edu break; 4265647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4275647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4285647Sgblack@eecs.umich.edu break; 4295647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4305647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4315647Sgblack@eecs.umich.edu break; 4325647Sgblack@eecs.umich.edu case APIC_EOI: 4335690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4345690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4355690Sgblack@eecs.umich.edu updateISRV(); 4365690Sgblack@eecs.umich.edu return; 4375647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4385647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4395647Sgblack@eecs.umich.edu break; 4405647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4415647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4425647Sgblack@eecs.umich.edu break; 4435647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4445647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4455647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4465647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4475647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4485647Sgblack@eecs.umich.edu break; 4495647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4505647Sgblack@eecs.umich.edu { 4515647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4525647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4535647Sgblack@eecs.umich.edu newVal = 0; 4545647Sgblack@eecs.umich.edu } else { 4555647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4565647Sgblack@eecs.umich.edu return; 4575647Sgblack@eecs.umich.edu } 4585647Sgblack@eecs.umich.edu 4595647Sgblack@eecs.umich.edu } 4605647Sgblack@eecs.umich.edu break; 4615647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4625647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Command low" 4635647Sgblack@eecs.umich.edu " register unimplemented.\n"); 4645647Sgblack@eecs.umich.edu break; 4655647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_HIGH: 4665647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Command high" 4675647Sgblack@eecs.umich.edu " register unimplemented.\n"); 4685647Sgblack@eecs.umich.edu break; 4695647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 4705647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 4715647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 4725647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 4735647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 4745647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 4755647Sgblack@eecs.umich.edu { 4765647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 4775647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 4785647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 4795647Sgblack@eecs.umich.edu } 4805647Sgblack@eecs.umich.edu break; 4815647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 4825648Sgblack@eecs.umich.edu { 4835648Sgblack@eecs.umich.edu assert(clock); 4845648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 4855848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 4865848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 4875848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 4885648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 4895848Sgblack@eecs.umich.edu Tick offset = curTick % clock; 4905648Sgblack@eecs.umich.edu if (offset) { 4915648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 4925848Sgblack@eecs.umich.edu curTick + (newCount + 1) * clock - offset, true); 4935648Sgblack@eecs.umich.edu } else { 4945648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 4955848Sgblack@eecs.umich.edu curTick + newCount * clock, true); 4965648Sgblack@eecs.umich.edu } 4975648Sgblack@eecs.umich.edu } 4985647Sgblack@eecs.umich.edu break; 4995647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 5005647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 5015647Sgblack@eecs.umich.edu return; 5025647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 5035647Sgblack@eecs.umich.edu newVal = val & 0xB; 5045647Sgblack@eecs.umich.edu break; 5055647Sgblack@eecs.umich.edu default: 5065647Sgblack@eecs.umich.edu break; 5075647Sgblack@eecs.umich.edu } 5085648Sgblack@eecs.umich.edu regs[reg] = newVal; 5095647Sgblack@eecs.umich.edu return; 5105647Sgblack@eecs.umich.edu} 5115647Sgblack@eecs.umich.edu 5126041Sgblack@eecs.umich.edu 5136041Sgblack@eecs.umich.eduX86ISA::Interrupts::Interrupts(Params * p) : 5146041Sgblack@eecs.umich.edu BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0), 5156041Sgblack@eecs.umich.edu apicTimerEvent(this), 5166041Sgblack@eecs.umich.edu pendingSmi(false), smiVector(0), 5176041Sgblack@eecs.umich.edu pendingNmi(false), nmiVector(0), 5186041Sgblack@eecs.umich.edu pendingExtInt(false), extIntVector(0), 5196041Sgblack@eecs.umich.edu pendingInit(false), initVector(0), 5206041Sgblack@eecs.umich.edu pendingUnmaskableInt(false) 5216041Sgblack@eecs.umich.edu{ 5226041Sgblack@eecs.umich.edu pioSize = PageBytes; 5236041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 5246041Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 5256041Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 5266041Sgblack@eecs.umich.edu ISRV = 0; 5276041Sgblack@eecs.umich.edu IRRV = 0; 5286041Sgblack@eecs.umich.edu} 5296041Sgblack@eecs.umich.edu 5306041Sgblack@eecs.umich.edu 5315654Sgblack@eecs.umich.edubool 5325704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 5335654Sgblack@eecs.umich.edu{ 5345654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 5355689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 5365689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 5375654Sgblack@eecs.umich.edu return true; 5385689Sgblack@eecs.umich.edu } 5395655Sgblack@eecs.umich.edu if (rflags.intf) { 5405689Sgblack@eecs.umich.edu if (pendingExtInt) { 5415689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 5425655Sgblack@eecs.umich.edu return true; 5435689Sgblack@eecs.umich.edu } 5445655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 5455689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 5465689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 5475655Sgblack@eecs.umich.edu return true; 5485689Sgblack@eecs.umich.edu } 5495654Sgblack@eecs.umich.edu } 5505654Sgblack@eecs.umich.edu return false; 5515654Sgblack@eecs.umich.edu} 5525654Sgblack@eecs.umich.edu 5535654Sgblack@eecs.umich.eduFault 5545704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 5555654Sgblack@eecs.umich.edu{ 5565704Snate@binkert.org assert(checkInterrupts(tc)); 5575655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 5585655Sgblack@eecs.umich.edu // check for. 5595655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 5605655Sgblack@eecs.umich.edu if (pendingSmi) { 5615689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 5625655Sgblack@eecs.umich.edu return new SystemManagementInterrupt(); 5635655Sgblack@eecs.umich.edu } else if (pendingNmi) { 5645689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 5655691Sgblack@eecs.umich.edu return new NonMaskableInterrupt(nmiVector); 5665655Sgblack@eecs.umich.edu } else if (pendingInit) { 5675689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 5685691Sgblack@eecs.umich.edu return new InitInterrupt(initVector); 5695655Sgblack@eecs.umich.edu } else { 5705655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 5715655Sgblack@eecs.umich.edu "ints were pending.\n"); 5725655Sgblack@eecs.umich.edu return NoFault; 5735655Sgblack@eecs.umich.edu } 5745655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 5755689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 5765691Sgblack@eecs.umich.edu return new ExternalInterrupt(extIntVector); 5775655Sgblack@eecs.umich.edu } else { 5785689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 5795655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 5805655Sgblack@eecs.umich.edu return new ExternalInterrupt(IRRV); 5815655Sgblack@eecs.umich.edu } 5825654Sgblack@eecs.umich.edu} 5835654Sgblack@eecs.umich.edu 5845654Sgblack@eecs.umich.eduvoid 5855704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 5865654Sgblack@eecs.umich.edu{ 5875704Snate@binkert.org assert(checkInterrupts(tc)); 5885655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 5895655Sgblack@eecs.umich.edu if (pendingSmi) { 5905689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 5915655Sgblack@eecs.umich.edu pendingSmi = false; 5925655Sgblack@eecs.umich.edu } else if (pendingNmi) { 5935689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 5945655Sgblack@eecs.umich.edu pendingNmi = false; 5955655Sgblack@eecs.umich.edu } else if (pendingInit) { 5965689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 5975655Sgblack@eecs.umich.edu pendingInit = false; 5985655Sgblack@eecs.umich.edu } 5995655Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit)) 6005655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 6015655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6025655Sgblack@eecs.umich.edu pendingExtInt = false; 6035655Sgblack@eecs.umich.edu } else { 6045689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 6055655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 6065655Sgblack@eecs.umich.edu ISRV = IRRV; 6075655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 6085655Sgblack@eecs.umich.edu // Clear it out of the IRR. 6095655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 6105655Sgblack@eecs.umich.edu updateIRRV(); 6115655Sgblack@eecs.umich.edu } 6125654Sgblack@eecs.umich.edu} 6135654Sgblack@eecs.umich.edu 6145647Sgblack@eecs.umich.eduX86ISA::Interrupts * 6155647Sgblack@eecs.umich.eduX86LocalApicParams::create() 6165647Sgblack@eecs.umich.edu{ 6175647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 6185647Sgblack@eecs.umich.edu} 619