interrupts.cc revision 11479
15647Sgblack@eecs.umich.edu/* 29544Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 145647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 155647Sgblack@eecs.umich.edu * All rights reserved. 165647Sgblack@eecs.umich.edu * 177087Snate@binkert.org * The license below extends only to copyright in the software and shall 187087Snate@binkert.org * not be construed as granting a license to any other intellectual 197087Snate@binkert.org * property including but not limited to intellectual property relating 207087Snate@binkert.org * to a hardware implementation of the functionality of the software 217087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 227087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 237087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 247087Snate@binkert.org * modified or unmodified, in source code or in binary form. 255647Sgblack@eecs.umich.edu * 267087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 277087Snate@binkert.org * modification, are permitted provided that the following conditions are 287087Snate@binkert.org * met: redistributions of source code must retain the above copyright 297087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 307087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 317087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 327087Snate@binkert.org * documentation and/or other materials provided with the distribution; 337087Snate@binkert.org * neither the name of the copyright holders nor the names of its 345647Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 357087Snate@binkert.org * this software without specific prior written permission. 365647Sgblack@eecs.umich.edu * 375647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 385647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 395647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 405647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 415647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 425647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 435647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 445647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 455647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 465647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 475647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 485647Sgblack@eecs.umich.edu * 495647Sgblack@eecs.umich.edu * Authors: Gabe Black 505647Sgblack@eecs.umich.edu */ 515647Sgblack@eecs.umich.edu 5210474Sandreas.hansson@arm.com#include <memory> 5310474Sandreas.hansson@arm.com 548229Snate@binkert.org#include "arch/x86/regs/apic.hh" 555647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 565654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 575647Sgblack@eecs.umich.edu#include "cpu/base.hh" 588232Snate@binkert.org#include "debug/LocalApic.hh" 596137Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 606137Sgblack@eecs.umich.edu#include "dev/x86/pc.hh" 616137Sgblack@eecs.umich.edu#include "dev/x86/south_bridge.hh" 625654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 636046Sgblack@eecs.umich.edu#include "sim/system.hh" 648781Sgblack@eecs.umich.edu#include "sim/full_system.hh" 655647Sgblack@eecs.umich.edu 665648Sgblack@eecs.umich.eduint 675648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 685647Sgblack@eecs.umich.edu{ 695647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 705647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 715647Sgblack@eecs.umich.edu // be deciphered fairly easily. 725647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 735647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 745647Sgblack@eecs.umich.edu return 1 << shift; 755647Sgblack@eecs.umich.edu} 765647Sgblack@eecs.umich.edu 775648Sgblack@eecs.umich.edunamespace X86ISA 785647Sgblack@eecs.umich.edu{ 795648Sgblack@eecs.umich.edu 805648Sgblack@eecs.umich.eduApicRegIndex 815648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 825648Sgblack@eecs.umich.edu{ 835648Sgblack@eecs.umich.edu ApicRegIndex regNum; 845648Sgblack@eecs.umich.edu paddr &= ~mask(3); 855648Sgblack@eecs.umich.edu switch (paddr) 865648Sgblack@eecs.umich.edu { 875648Sgblack@eecs.umich.edu case 0x20: 885648Sgblack@eecs.umich.edu regNum = APIC_ID; 895648Sgblack@eecs.umich.edu break; 905648Sgblack@eecs.umich.edu case 0x30: 915648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 925648Sgblack@eecs.umich.edu break; 935648Sgblack@eecs.umich.edu case 0x80: 945648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 955648Sgblack@eecs.umich.edu break; 965648Sgblack@eecs.umich.edu case 0x90: 975648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 985648Sgblack@eecs.umich.edu break; 995648Sgblack@eecs.umich.edu case 0xA0: 1005648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 1015648Sgblack@eecs.umich.edu break; 1025648Sgblack@eecs.umich.edu case 0xB0: 1035648Sgblack@eecs.umich.edu regNum = APIC_EOI; 1045648Sgblack@eecs.umich.edu break; 1055648Sgblack@eecs.umich.edu case 0xD0: 1065648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 1075648Sgblack@eecs.umich.edu break; 1085648Sgblack@eecs.umich.edu case 0xE0: 1095648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 1105648Sgblack@eecs.umich.edu break; 1115648Sgblack@eecs.umich.edu case 0xF0: 1125648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 1135648Sgblack@eecs.umich.edu break; 1145648Sgblack@eecs.umich.edu case 0x100: 1155648Sgblack@eecs.umich.edu case 0x110: 1165648Sgblack@eecs.umich.edu case 0x120: 1175648Sgblack@eecs.umich.edu case 0x130: 1185648Sgblack@eecs.umich.edu case 0x140: 1195648Sgblack@eecs.umich.edu case 0x150: 1205648Sgblack@eecs.umich.edu case 0x160: 1215648Sgblack@eecs.umich.edu case 0x170: 12211479Sbaz21@cam.ac.uk regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x10); 1235648Sgblack@eecs.umich.edu break; 1245648Sgblack@eecs.umich.edu case 0x180: 1255648Sgblack@eecs.umich.edu case 0x190: 1265648Sgblack@eecs.umich.edu case 0x1A0: 1275648Sgblack@eecs.umich.edu case 0x1B0: 1285648Sgblack@eecs.umich.edu case 0x1C0: 1295648Sgblack@eecs.umich.edu case 0x1D0: 1305648Sgblack@eecs.umich.edu case 0x1E0: 1315648Sgblack@eecs.umich.edu case 0x1F0: 13211479Sbaz21@cam.ac.uk regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x10); 1335648Sgblack@eecs.umich.edu break; 1345648Sgblack@eecs.umich.edu case 0x200: 1355648Sgblack@eecs.umich.edu case 0x210: 1365648Sgblack@eecs.umich.edu case 0x220: 1375648Sgblack@eecs.umich.edu case 0x230: 1385648Sgblack@eecs.umich.edu case 0x240: 1395648Sgblack@eecs.umich.edu case 0x250: 1405648Sgblack@eecs.umich.edu case 0x260: 1415648Sgblack@eecs.umich.edu case 0x270: 14211479Sbaz21@cam.ac.uk regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x10); 1435648Sgblack@eecs.umich.edu break; 1445648Sgblack@eecs.umich.edu case 0x280: 1455648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1465648Sgblack@eecs.umich.edu break; 1475648Sgblack@eecs.umich.edu case 0x300: 1485648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1495648Sgblack@eecs.umich.edu break; 1505648Sgblack@eecs.umich.edu case 0x310: 1515648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1525648Sgblack@eecs.umich.edu break; 1535648Sgblack@eecs.umich.edu case 0x320: 1545648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1555648Sgblack@eecs.umich.edu break; 1565648Sgblack@eecs.umich.edu case 0x330: 1575648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1585648Sgblack@eecs.umich.edu break; 1595648Sgblack@eecs.umich.edu case 0x340: 1605648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1615648Sgblack@eecs.umich.edu break; 1625648Sgblack@eecs.umich.edu case 0x350: 1635648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1645648Sgblack@eecs.umich.edu break; 1655648Sgblack@eecs.umich.edu case 0x360: 1665648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1675648Sgblack@eecs.umich.edu break; 1685648Sgblack@eecs.umich.edu case 0x370: 1695648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1705648Sgblack@eecs.umich.edu break; 1715648Sgblack@eecs.umich.edu case 0x380: 1725648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1735648Sgblack@eecs.umich.edu break; 1745648Sgblack@eecs.umich.edu case 0x390: 1755648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1765648Sgblack@eecs.umich.edu break; 1775648Sgblack@eecs.umich.edu case 0x3E0: 1785648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 1795648Sgblack@eecs.umich.edu break; 1805648Sgblack@eecs.umich.edu default: 1815648Sgblack@eecs.umich.edu // A reserved register field. 1825648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 1835648Sgblack@eecs.umich.edu break; 1845648Sgblack@eecs.umich.edu } 1855648Sgblack@eecs.umich.edu return regNum; 1865648Sgblack@eecs.umich.edu} 1875648Sgblack@eecs.umich.edu} 1885648Sgblack@eecs.umich.edu 1895648Sgblack@eecs.umich.eduTick 1905648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 1915648Sgblack@eecs.umich.edu{ 1925648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 1935648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 1945648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 1955648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 1965648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 1975648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 1985649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 1995649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2005649Sgblack@eecs.umich.edu reg, offset, val); 2015648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2025898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2039805Sstever@gmail.com return pioDelay; 2045648Sgblack@eecs.umich.edu} 2055648Sgblack@eecs.umich.edu 2065648Sgblack@eecs.umich.eduTick 2075648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2085648Sgblack@eecs.umich.edu{ 2095648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2105648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2115648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2125648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2135648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2145648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2155648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2165649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2175649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2185649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2195648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2205898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2219805Sstever@gmail.com return pioDelay; 2225647Sgblack@eecs.umich.edu} 2235691Sgblack@eecs.umich.eduvoid 2245691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2255691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2265691Sgblack@eecs.umich.edu{ 2275691Sgblack@eecs.umich.edu /* 2285691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2295691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2305691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2315691Sgblack@eecs.umich.edu */ 2325691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2335691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2345691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2355691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2365691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2375691Sgblack@eecs.umich.edu if (vector > IRRV) 2385691Sgblack@eecs.umich.edu IRRV = vector; 2395691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2405691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2415691Sgblack@eecs.umich.edu if (level) { 2425691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2435691Sgblack@eecs.umich.edu } else { 2445691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2455691Sgblack@eecs.umich.edu } 2465691Sgblack@eecs.umich.edu } 2475691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2485691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2495691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2505691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2515691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2525691Sgblack@eecs.umich.edu smiVector = vector; 2535691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2545691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2555691Sgblack@eecs.umich.edu nmiVector = vector; 2565691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2575691Sgblack@eecs.umich.edu pendingExtInt = true; 2585691Sgblack@eecs.umich.edu extIntVector = vector; 2595691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2605691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2615691Sgblack@eecs.umich.edu initVector = vector; 2626066Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && 2636066Sgblack@eecs.umich.edu !pendingStartup && !startedUp) { 2646050Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2656050Sgblack@eecs.umich.edu startupVector = vector; 2665691Sgblack@eecs.umich.edu } 2678745Sgblack@eecs.umich.edu } 2688781Sgblack@eecs.umich.edu if (FullSystem) 26911151Smitch.hayenga@arm.com cpu->wakeup(0); 2705691Sgblack@eecs.umich.edu} 2715647Sgblack@eecs.umich.edu 2726041Sgblack@eecs.umich.edu 2736041Sgblack@eecs.umich.eduvoid 2746041Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2756041Sgblack@eecs.umich.edu{ 2766136Sgblack@eecs.umich.edu assert(newCPU); 2776136Sgblack@eecs.umich.edu if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 2786136Sgblack@eecs.umich.edu panic("Local APICs can't be moved between CPUs" 2796136Sgblack@eecs.umich.edu " with different IDs.\n"); 2806136Sgblack@eecs.umich.edu } 2816041Sgblack@eecs.umich.edu cpu = newCPU; 2826136Sgblack@eecs.umich.edu initialApicId = cpu->cpuId(); 2836136Sgblack@eecs.umich.edu regs[APIC_ID] = (initialApicId << 24); 2849090Sandreas.hansson@arm.com pioAddr = x86LocalAPICAddress(initialApicId, 0); 2856041Sgblack@eecs.umich.edu} 2866041Sgblack@eecs.umich.edu 2876041Sgblack@eecs.umich.edu 2886137Sgblack@eecs.umich.eduvoid 2896137Sgblack@eecs.umich.eduX86ISA::Interrupts::init() 2906137Sgblack@eecs.umich.edu{ 2917913SBrad.Beckmann@amd.com // 2929807Sstever@gmail.com // The local apic must register its address ranges on both its pio 2939807Sstever@gmail.com // port via the basicpiodevice(piodevice) init() function and its 2949807Sstever@gmail.com // int port that it inherited from IntDevice. Note IntDevice is 2959807Sstever@gmail.com // not a SimObject itself. 2967913SBrad.Beckmann@amd.com // 2976137Sgblack@eecs.umich.edu BasicPioDevice::init(); 2989807Sstever@gmail.com IntDevice::init(); 2998922Swilliam.wang@arm.com 3008922Swilliam.wang@arm.com // the slave port has a range so inform the connected master 3018922Swilliam.wang@arm.com intSlavePort.sendRangeChange(); 3026137Sgblack@eecs.umich.edu} 3036137Sgblack@eecs.umich.edu 3046137Sgblack@eecs.umich.edu 3055651Sgblack@eecs.umich.eduTick 3065651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3075651Sgblack@eecs.umich.edu{ 3086136Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 3095651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3105651Sgblack@eecs.umich.edu switch(offset) 3115651Sgblack@eecs.umich.edu { 3125651Sgblack@eecs.umich.edu case 0: 3135654Sgblack@eecs.umich.edu { 3145654Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3155654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3165654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3175697Snate@binkert.org message.vector); 3185655Sgblack@eecs.umich.edu 3195691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3205691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3215654Sgblack@eecs.umich.edu } 3225651Sgblack@eecs.umich.edu break; 3235651Sgblack@eecs.umich.edu default: 3245651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3255651Sgblack@eecs.umich.edu offset); 3265651Sgblack@eecs.umich.edu break; 3275651Sgblack@eecs.umich.edu } 3286064Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 3299805Sstever@gmail.com return pioDelay; 3305651Sgblack@eecs.umich.edu} 3315651Sgblack@eecs.umich.edu 3325651Sgblack@eecs.umich.edu 3336065Sgblack@eecs.umich.eduTick 3346065Sgblack@eecs.umich.eduX86ISA::Interrupts::recvResponse(PacketPtr pkt) 3356065Sgblack@eecs.umich.edu{ 3366065Sgblack@eecs.umich.edu assert(!pkt->isError()); 3376065Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageResp); 3386069Sgblack@eecs.umich.edu if (--pendingIPIs == 0) { 3396069Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 3406069Sgblack@eecs.umich.edu // Record that the ICR is now idle. 3416069Sgblack@eecs.umich.edu low.deliveryStatus = 0; 3426069Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 3436069Sgblack@eecs.umich.edu } 3446065Sgblack@eecs.umich.edu DPRINTF(LocalApic, "ICR is now idle.\n"); 3456065Sgblack@eecs.umich.edu return 0; 3466065Sgblack@eecs.umich.edu} 3476065Sgblack@eecs.umich.edu 3486065Sgblack@eecs.umich.edu 3498711Sandreas.hansson@arm.comAddrRangeList 3509090Sandreas.hansson@arm.comX86ISA::Interrupts::getIntAddrRange() const 3516041Sgblack@eecs.umich.edu{ 3528711Sandreas.hansson@arm.com AddrRangeList ranges; 3538711Sandreas.hansson@arm.com ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 3548711Sandreas.hansson@arm.com x86InterruptAddress(initialApicId, 0) + 3558711Sandreas.hansson@arm.com PhysAddrAPICRangeSize)); 3568711Sandreas.hansson@arm.com return ranges; 3576041Sgblack@eecs.umich.edu} 3586041Sgblack@eecs.umich.edu 3596041Sgblack@eecs.umich.edu 3605647Sgblack@eecs.umich.eduuint32_t 3615648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3625647Sgblack@eecs.umich.edu{ 3635647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3645647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3655647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3665647Sgblack@eecs.umich.edu } 3675647Sgblack@eecs.umich.edu switch (reg) { 3685647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3695647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3705647Sgblack@eecs.umich.edu break; 3715647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 3725647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 3735647Sgblack@eecs.umich.edu break; 3745647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 3755647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 3765647Sgblack@eecs.umich.edu break; 3775647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 3785647Sgblack@eecs.umich.edu { 3795848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 3805848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 3819544Sandreas.hansson@arm.com uint64_t ticksPerCount = clockPeriod() * 3825848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 3835848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 3847823Ssteve.reinhardt@amd.com uint64_t val = apicTimerEvent.when() - curTick(); 3855848Sgblack@eecs.umich.edu // Turn that into a count. 3865848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 3875848Sgblack@eecs.umich.edu return val; 3885848Sgblack@eecs.umich.edu } else { 3895848Sgblack@eecs.umich.edu return 0; 3905848Sgblack@eecs.umich.edu } 3915647Sgblack@eecs.umich.edu } 3925647Sgblack@eecs.umich.edu default: 3935647Sgblack@eecs.umich.edu break; 3945647Sgblack@eecs.umich.edu } 3955648Sgblack@eecs.umich.edu return regs[reg]; 3965647Sgblack@eecs.umich.edu} 3975647Sgblack@eecs.umich.edu 3985647Sgblack@eecs.umich.eduvoid 3995648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 4005647Sgblack@eecs.umich.edu{ 4015647Sgblack@eecs.umich.edu uint32_t newVal = val; 4025647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4035647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4045647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4055647Sgblack@eecs.umich.edu } 4065647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4075647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4085647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4095647Sgblack@eecs.umich.edu } 4105647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4115647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4125647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4135647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4145647Sgblack@eecs.umich.edu } 4155647Sgblack@eecs.umich.edu switch (reg) { 4165647Sgblack@eecs.umich.edu case APIC_ID: 4175647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4185647Sgblack@eecs.umich.edu break; 4195647Sgblack@eecs.umich.edu case APIC_VERSION: 4205647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4215647Sgblack@eecs.umich.edu return; 4225647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4235647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4245647Sgblack@eecs.umich.edu break; 4255647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4265647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4275647Sgblack@eecs.umich.edu break; 4285647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4295647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4305647Sgblack@eecs.umich.edu break; 4315647Sgblack@eecs.umich.edu case APIC_EOI: 4325690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4335690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4345690Sgblack@eecs.umich.edu updateISRV(); 4355690Sgblack@eecs.umich.edu return; 4365647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4375647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4385647Sgblack@eecs.umich.edu break; 4395647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4405647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4415647Sgblack@eecs.umich.edu break; 4425647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4435647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4445647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4455647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4465647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4475647Sgblack@eecs.umich.edu break; 4485647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4495647Sgblack@eecs.umich.edu { 4505647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4515647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4525647Sgblack@eecs.umich.edu newVal = 0; 4535647Sgblack@eecs.umich.edu } else { 4545647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4555647Sgblack@eecs.umich.edu return; 4565647Sgblack@eecs.umich.edu } 4575647Sgblack@eecs.umich.edu 4585647Sgblack@eecs.umich.edu } 4595647Sgblack@eecs.umich.edu break; 4605647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4616046Sgblack@eecs.umich.edu { 4626046Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 4636046Sgblack@eecs.umich.edu // Check if we're already sending an IPI. 4646046Sgblack@eecs.umich.edu if (low.deliveryStatus) { 4656046Sgblack@eecs.umich.edu newVal = low; 4666046Sgblack@eecs.umich.edu break; 4676046Sgblack@eecs.umich.edu } 4686046Sgblack@eecs.umich.edu low = val; 4696046Sgblack@eecs.umich.edu InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 4706712Snate@binkert.org TriggerIntMessage message = 0; 4716046Sgblack@eecs.umich.edu message.destination = high.destination; 4726046Sgblack@eecs.umich.edu message.vector = low.vector; 4736046Sgblack@eecs.umich.edu message.deliveryMode = low.deliveryMode; 4746046Sgblack@eecs.umich.edu message.destMode = low.destMode; 4756046Sgblack@eecs.umich.edu message.level = low.level; 4766046Sgblack@eecs.umich.edu message.trigger = low.trigger; 4776138Sgblack@eecs.umich.edu ApicList apics; 4786138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 4796046Sgblack@eecs.umich.edu switch (low.destShorthand) { 4806046Sgblack@eecs.umich.edu case 0: 4816138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 4826138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode " 4836138Sgblack@eecs.umich.edu "IPIs aren't implemented.\n"); 4846138Sgblack@eecs.umich.edu } 4856138Sgblack@eecs.umich.edu if (message.destMode == 1) { 4866138Sgblack@eecs.umich.edu int dest = message.destination; 4876138Sgblack@eecs.umich.edu hack_once("Assuming logical destinations are 1 << id.\n"); 4886138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 4896138Sgblack@eecs.umich.edu if (dest & 0x1) 4906138Sgblack@eecs.umich.edu apics.push_back(i); 4916138Sgblack@eecs.umich.edu dest = dest >> 1; 4926138Sgblack@eecs.umich.edu } 4936138Sgblack@eecs.umich.edu } else { 4946138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 4956138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 4966138Sgblack@eecs.umich.edu if (i == initialApicId) { 4976138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 4986138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 4996138Sgblack@eecs.umich.edu } else { 5006138Sgblack@eecs.umich.edu apics.push_back(i); 5016138Sgblack@eecs.umich.edu } 5026138Sgblack@eecs.umich.edu } 5036138Sgblack@eecs.umich.edu } else { 5046138Sgblack@eecs.umich.edu if (message.destination == initialApicId) { 5056138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5066138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5076138Sgblack@eecs.umich.edu } else { 5086138Sgblack@eecs.umich.edu apics.push_back(message.destination); 5096138Sgblack@eecs.umich.edu } 5106138Sgblack@eecs.umich.edu } 5116138Sgblack@eecs.umich.edu } 5126046Sgblack@eecs.umich.edu break; 5136046Sgblack@eecs.umich.edu case 1: 5146069Sgblack@eecs.umich.edu newVal = val; 5156069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5166069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5176046Sgblack@eecs.umich.edu break; 5186046Sgblack@eecs.umich.edu case 2: 5196069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5206069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5216069Sgblack@eecs.umich.edu // Fall through 5226046Sgblack@eecs.umich.edu case 3: 5236069Sgblack@eecs.umich.edu { 5246069Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5256138Sgblack@eecs.umich.edu if (i != initialApicId) { 5266138Sgblack@eecs.umich.edu apics.push_back(i); 5276069Sgblack@eecs.umich.edu } 5286069Sgblack@eecs.umich.edu } 5296069Sgblack@eecs.umich.edu } 5306046Sgblack@eecs.umich.edu break; 5316046Sgblack@eecs.umich.edu } 53210542Sgabeblack@google.com // Record that an IPI is being sent if one actually is. 53310542Sgabeblack@google.com if (apics.size()) { 53410542Sgabeblack@google.com low.deliveryStatus = 1; 53510542Sgabeblack@google.com pendingIPIs += apics.size(); 53610542Sgabeblack@google.com } 53710542Sgabeblack@google.com regs[APIC_INTERRUPT_COMMAND_LOW] = low; 53810542Sgabeblack@google.com intMasterPort.sendMessage(apics, message, sys->isTimingMode()); 5396138Sgblack@eecs.umich.edu newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 5406046Sgblack@eecs.umich.edu } 5415647Sgblack@eecs.umich.edu break; 5425647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 5435647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 5445647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 5455647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 5465647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 5475647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 5485647Sgblack@eecs.umich.edu { 5495647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 5505647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 5515647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 5525647Sgblack@eecs.umich.edu } 5535647Sgblack@eecs.umich.edu break; 5545647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 5555648Sgblack@eecs.umich.edu { 5565648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 5575848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 5585848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 5595848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 5605648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 5619544Sandreas.hansson@arm.com Tick offset = curTick() % clockPeriod(); 5625648Sgblack@eecs.umich.edu if (offset) { 5635648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5649544Sandreas.hansson@arm.com curTick() + (newCount + 1) * 5659544Sandreas.hansson@arm.com clockPeriod() - offset, true); 5665648Sgblack@eecs.umich.edu } else { 5679623Snilay@cs.wisc.edu if (newCount) 5689623Snilay@cs.wisc.edu reschedule(apicTimerEvent, 5699623Snilay@cs.wisc.edu curTick() + newCount * 5709623Snilay@cs.wisc.edu clockPeriod(), true); 5715648Sgblack@eecs.umich.edu } 5725648Sgblack@eecs.umich.edu } 5735647Sgblack@eecs.umich.edu break; 5745647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 5755647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 5765647Sgblack@eecs.umich.edu return; 5775647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 5785647Sgblack@eecs.umich.edu newVal = val & 0xB; 5795647Sgblack@eecs.umich.edu break; 5805647Sgblack@eecs.umich.edu default: 5815647Sgblack@eecs.umich.edu break; 5825647Sgblack@eecs.umich.edu } 5835648Sgblack@eecs.umich.edu regs[reg] = newVal; 5845647Sgblack@eecs.umich.edu return; 5855647Sgblack@eecs.umich.edu} 5865647Sgblack@eecs.umich.edu 5876041Sgblack@eecs.umich.edu 5889807Sstever@gmail.comX86ISA::Interrupts::Interrupts(Params * p) 5899808Sstever@gmail.com : BasicPioDevice(p, PageBytes), IntDevice(this, p->int_latency), 5909807Sstever@gmail.com apicTimerEvent(this), 5919807Sstever@gmail.com pendingSmi(false), smiVector(0), 5929807Sstever@gmail.com pendingNmi(false), nmiVector(0), 5939807Sstever@gmail.com pendingExtInt(false), extIntVector(0), 5949807Sstever@gmail.com pendingInit(false), initVector(0), 5959807Sstever@gmail.com pendingStartup(false), startupVector(0), 5969807Sstever@gmail.com startedUp(false), pendingUnmaskableInt(false), 5979807Sstever@gmail.com pendingIPIs(0), cpu(NULL), 5989807Sstever@gmail.com intSlavePort(name() + ".int_slave", this, this) 5996041Sgblack@eecs.umich.edu{ 6006041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 6016041Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 6026041Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 6036041Sgblack@eecs.umich.edu ISRV = 0; 6046041Sgblack@eecs.umich.edu IRRV = 0; 6056041Sgblack@eecs.umich.edu} 6066041Sgblack@eecs.umich.edu 6076041Sgblack@eecs.umich.edu 6085654Sgblack@eecs.umich.edubool 6095704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 6105654Sgblack@eecs.umich.edu{ 6115654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 6125689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6135689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 6145654Sgblack@eecs.umich.edu return true; 6155689Sgblack@eecs.umich.edu } 6165655Sgblack@eecs.umich.edu if (rflags.intf) { 6175689Sgblack@eecs.umich.edu if (pendingExtInt) { 6185689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 6195655Sgblack@eecs.umich.edu return true; 6205689Sgblack@eecs.umich.edu } 6215655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 6225689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 6235689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 6245655Sgblack@eecs.umich.edu return true; 6255689Sgblack@eecs.umich.edu } 6265654Sgblack@eecs.umich.edu } 6275654Sgblack@eecs.umich.edu return false; 6285654Sgblack@eecs.umich.edu} 6295654Sgblack@eecs.umich.edu 6309874Sandreas@sandberg.pp.sebool 6319874Sandreas@sandberg.pp.seX86ISA::Interrupts::checkInterruptsRaw() const 6329874Sandreas@sandberg.pp.se{ 6339874Sandreas@sandberg.pp.se return pendingUnmaskableInt || pendingExtInt || 6349874Sandreas@sandberg.pp.se (IRRV > ISRV && bits(IRRV, 7, 4) > 6359874Sandreas@sandberg.pp.se bits(regs[APIC_TASK_PRIORITY], 7, 4)); 6369874Sandreas@sandberg.pp.se} 6379874Sandreas@sandberg.pp.se 6385654Sgblack@eecs.umich.eduFault 6395704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 6405654Sgblack@eecs.umich.edu{ 6415704Snate@binkert.org assert(checkInterrupts(tc)); 6425655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 6435655Sgblack@eecs.umich.edu // check for. 6445655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6455655Sgblack@eecs.umich.edu if (pendingSmi) { 6465689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 64710474Sandreas.hansson@arm.com return std::make_shared<SystemManagementInterrupt>(); 6485655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6495689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 65010474Sandreas.hansson@arm.com return std::make_shared<NonMaskableInterrupt>(nmiVector); 6515655Sgblack@eecs.umich.edu } else if (pendingInit) { 6525689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 65310474Sandreas.hansson@arm.com return std::make_shared<InitInterrupt>(initVector); 6546050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6556050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 65610474Sandreas.hansson@arm.com return std::make_shared<StartupInterrupt>(startupVector); 6575655Sgblack@eecs.umich.edu } else { 6585655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 6595655Sgblack@eecs.umich.edu "ints were pending.\n"); 6605655Sgblack@eecs.umich.edu return NoFault; 6615655Sgblack@eecs.umich.edu } 6625655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6635689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 66410474Sandreas.hansson@arm.com return std::make_shared<ExternalInterrupt>(extIntVector); 6655655Sgblack@eecs.umich.edu } else { 6665689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 6675655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 66810474Sandreas.hansson@arm.com return std::make_shared<ExternalInterrupt>(IRRV); 6695655Sgblack@eecs.umich.edu } 6705654Sgblack@eecs.umich.edu} 6715654Sgblack@eecs.umich.edu 6725654Sgblack@eecs.umich.eduvoid 6735704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 6745654Sgblack@eecs.umich.edu{ 6755704Snate@binkert.org assert(checkInterrupts(tc)); 6765655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6775655Sgblack@eecs.umich.edu if (pendingSmi) { 6785689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 6795655Sgblack@eecs.umich.edu pendingSmi = false; 6805655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6815689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 6825655Sgblack@eecs.umich.edu pendingNmi = false; 6835655Sgblack@eecs.umich.edu } else if (pendingInit) { 6845689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 6855655Sgblack@eecs.umich.edu pendingInit = false; 6866066Sgblack@eecs.umich.edu startedUp = false; 6876050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6886050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SIPI sent to core.\n"); 6896050Sgblack@eecs.umich.edu pendingStartup = false; 6906066Sgblack@eecs.umich.edu startedUp = true; 6915655Sgblack@eecs.umich.edu } 6926050Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 6935655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 6945655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6955655Sgblack@eecs.umich.edu pendingExtInt = false; 6965655Sgblack@eecs.umich.edu } else { 6975689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 6985655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 6995655Sgblack@eecs.umich.edu ISRV = IRRV; 7005655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 7015655Sgblack@eecs.umich.edu // Clear it out of the IRR. 7025655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 7035655Sgblack@eecs.umich.edu updateIRRV(); 7045655Sgblack@eecs.umich.edu } 7055654Sgblack@eecs.umich.edu} 7065654Sgblack@eecs.umich.edu 7077902Shestness@cs.utexas.eduvoid 70810905Sandreas.sandberg@arm.comX86ISA::Interrupts::serialize(CheckpointOut &cp) const 7097902Shestness@cs.utexas.edu{ 7107902Shestness@cs.utexas.edu SERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7117902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingSmi); 7127902Shestness@cs.utexas.edu SERIALIZE_SCALAR(smiVector); 7137902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingNmi); 7147902Shestness@cs.utexas.edu SERIALIZE_SCALAR(nmiVector); 7157902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingExtInt); 7167902Shestness@cs.utexas.edu SERIALIZE_SCALAR(extIntVector); 7177902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingInit); 7187902Shestness@cs.utexas.edu SERIALIZE_SCALAR(initVector); 7197902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingStartup); 7207902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startupVector); 7217902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startedUp); 7227902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingUnmaskableInt); 7237902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingIPIs); 7247902Shestness@cs.utexas.edu SERIALIZE_SCALAR(IRRV); 7257902Shestness@cs.utexas.edu SERIALIZE_SCALAR(ISRV); 7267902Shestness@cs.utexas.edu bool apicTimerEventScheduled = apicTimerEvent.scheduled(); 7277902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventScheduled); 7287902Shestness@cs.utexas.edu Tick apicTimerEventTick = apicTimerEvent.when(); 7297902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventTick); 7307902Shestness@cs.utexas.edu} 7317902Shestness@cs.utexas.edu 7327902Shestness@cs.utexas.eduvoid 73310905Sandreas.sandberg@arm.comX86ISA::Interrupts::unserialize(CheckpointIn &cp) 7347902Shestness@cs.utexas.edu{ 7357902Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7367902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingSmi); 7377902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(smiVector); 7387902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingNmi); 7397902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(nmiVector); 7407902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingExtInt); 7417902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(extIntVector); 7427902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingInit); 7437902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initVector); 7447902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingStartup); 7457902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startupVector); 7467902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startedUp); 7477902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingUnmaskableInt); 7487902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingIPIs); 7497902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(IRRV); 7507902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(ISRV); 7517902Shestness@cs.utexas.edu bool apicTimerEventScheduled; 7527902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventScheduled); 7537902Shestness@cs.utexas.edu if (apicTimerEventScheduled) { 7547902Shestness@cs.utexas.edu Tick apicTimerEventTick; 7557902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventTick); 7567902Shestness@cs.utexas.edu if (apicTimerEvent.scheduled()) { 7577902Shestness@cs.utexas.edu reschedule(apicTimerEvent, apicTimerEventTick, true); 7587902Shestness@cs.utexas.edu } else { 7597902Shestness@cs.utexas.edu schedule(apicTimerEvent, apicTimerEventTick); 7607902Shestness@cs.utexas.edu } 7617902Shestness@cs.utexas.edu } 7627902Shestness@cs.utexas.edu} 7637902Shestness@cs.utexas.edu 7645647Sgblack@eecs.umich.eduX86ISA::Interrupts * 7655647Sgblack@eecs.umich.eduX86LocalApicParams::create() 7665647Sgblack@eecs.umich.edu{ 7675647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 7685647Sgblack@eecs.umich.edu} 769