microregop.hh revision 4713
16145SN/A/* 26386SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company 37553SN/A * All rights reserved. 46386SN/A * 56386SN/A * Redistribution and use of this software in source and binary forms, 66386SN/A * with or without modification, are permitted provided that the 76386SN/A * following conditions are met: 86386SN/A * 96386SN/A * The software must be used only for Non-Commercial Use which means any 106386SN/A * use which is NOT directed to receiving any direct monetary 116386SN/A * compensation for, or commercial advantage from such use. Illustrative 126386SN/A * examples of non-commercial use are academic research, personal study, 136386SN/A * teaching, education and corporate research & development. 146386SN/A * Illustrative examples of commercial use are distributing products for 156386SN/A * commercial advantage and providing services using the software for 166386SN/A * commercial advantage. 176386SN/A * 186386SN/A * If you wish to use this software or functionality therein that may be 196386SN/A * covered by patents for commercial use, please contact: 206386SN/A * Director of Intellectual Property Licensing 216386SN/A * Office of Strategy and Technology 226386SN/A * Hewlett-Packard Company 236386SN/A * 1501 Page Mill Road 246386SN/A * Palo Alto, California 94304 256386SN/A * 266386SN/A * Redistributions of source code must retain the above copyright notice, 276386SN/A * this list of conditions and the following disclaimer. Redistributions 286386SN/A * in binary form must reproduce the above copyright notice, this list of 296145SN/A * conditions and the following disclaimer in the documentation and/or 3010348Sandreas.hansson@arm.com * other materials provided with the distribution. Neither the name of 317632SBrad.Beckmann@amd.com * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 327632SBrad.Beckmann@amd.com * contributors may be used to endorse or promote products derived from 337632SBrad.Beckmann@amd.com * this software without specific prior written permission. No right of 348232Snate@binkert.org * sublicense is granted herewith. Derivatives of the software and 356145SN/A * output created using the software may be prepared, but only for 367553SN/A * Non-Commercial Uses. Derivatives of the software may be shared with 379365Snilay@cs.wisc.edu * others provided: (i) the others agree to abide by the list of 389365Snilay@cs.wisc.edu * conditions herein which includes the Non-Commercial Use restrictions; 399365Snilay@cs.wisc.edu * and (ii) such Derivatives of the software include the above copyright 406145SN/A * notice to acknowledge the contribution from this software where 417553SN/A * applicable, this list of conditions and the disclaimer below. 427553SN/A * 437553SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 446145SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 456145SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 467553SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 476145SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 486145SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 496145SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 507553SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 517553SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 526145SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 537553SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 547553SN/A * 556145SN/A * Authors: Gabe Black 568950Sandreas.hansson@arm.com */ 577553SN/A 587553SN/A#ifndef __ARCH_X86_INSTS_MICROREGOP_HH__ 597553SN/A#define __ARCH_X86_INSTS_MICROREGOP_HH__ 607553SN/A 618832SAli.Saidi@ARM.com#include "arch/x86/insts/microop.hh" 627553SN/A 637553SN/Anamespace X86ISA 6410348Sandreas.hansson@arm.com{ 659365Snilay@cs.wisc.edu namespace ConditionTests 667553SN/A { 677553SN/A enum CondTest { 687553SN/A True, 696145SN/A NotFalse = True, 709365Snilay@cs.wisc.edu ECF, 718949Sandreas.hansson@arm.com EZF, 727553SN/A SZnZF, 737553SN/A MSTRZ, 747553SN/A STRZ, 756145SN/A MSTRC, 768975Sandreas.hansson@arm.com STRZnZF, 777553SN/A OF, 787553SN/A CF, 797553SN/A ZF, 807553SN/A CvZF, 817553SN/A SF, 827553SN/A PF, 837553SN/A SxOF, 847553SN/A SxOvZF, 857553SN/A 867553SN/A False, 877553SN/A NotTrue = False, 887553SN/A NotECF, 897553SN/A NotEZF, 906145SN/A NotSZnZF, 916145SN/A NotMSTRZ, 927553SN/A NotSTRZ, 938655Sandreas.hansson@arm.com NotMSTRC, 946145SN/A NotSTRZnZF, 957553SN/A NotOF, 967553SN/A NotCF, 977553SN/A NotZF, 986145SN/A NotCvZF, 997553SN/A NotSF, 1007553SN/A NotPF, 1017553SN/A NotSxOF, 1027553SN/A NotSxOvZF 1037553SN/A }; 1047553SN/A } 1057553SN/A 1067553SN/A /** 1077553SN/A * Base classes for RegOps which provides a generateDisassembly method. 1087553SN/A */ 1097553SN/A class RegOpBase : public X86MicroopBase 1106145SN/A { 1116145SN/A protected: 1127553SN/A const RegIndex src1; 1137553SN/A const RegIndex dest; 1146145SN/A const uint8_t dataSize; 1157553SN/A const uint16_t ext; 1166145SN/A 117 // Constructor 118 RegOpBase(ExtMachInst _machInst, 119 const char *mnem, const char *_instMnem, 120 bool isMicro, bool isDelayed, 121 bool isFirst, bool isLast, 122 RegIndex _src1, RegIndex _dest, 123 uint8_t _dataSize, uint16_t _ext, 124 OpClass __opClass) : 125 X86MicroopBase(_machInst, mnem, _instMnem, 126 isMicro, isDelayed, isFirst, isLast, 127 __opClass), 128 src1(_src1), dest(_dest), 129 dataSize(_dataSize), ext(_ext) 130 { 131 } 132 133 //Figure out what the condition code flags should be. 134 uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask, 135 uint64_t _dest, uint64_t _src1, uint64_t _src2, 136 bool subtract = false) const; 137 bool checkCondition(uint64_t flags) const; 138 }; 139 140 class RegOp : public RegOpBase 141 { 142 protected: 143 const RegIndex src2; 144 145 // Constructor 146 RegOp(ExtMachInst _machInst, 147 const char *mnem, const char *_instMnem, 148 bool isMicro, bool isDelayed, 149 bool isFirst, bool isLast, 150 RegIndex _src1, RegIndex _src2, RegIndex _dest, 151 uint8_t _dataSize, uint16_t _ext, 152 OpClass __opClass) : 153 RegOpBase(_machInst, mnem, _instMnem, 154 isMicro, isDelayed, isFirst, isLast, 155 _src1, _dest, _dataSize, _ext, 156 __opClass), 157 src2(_src2) 158 { 159 } 160 161 std::string generateDisassembly(Addr pc, 162 const SymbolTable *symtab) const; 163 }; 164 165 class RegOpImm : public RegOpBase 166 { 167 protected: 168 const uint8_t imm8; 169 170 // Constructor 171 RegOpImm(ExtMachInst _machInst, 172 const char * mnem, const char *_instMnem, 173 bool isMicro, bool isDelayed, 174 bool isFirst, bool isLast, 175 RegIndex _src1, uint8_t _imm8, RegIndex _dest, 176 uint8_t _dataSize, uint16_t _ext, 177 OpClass __opClass) : 178 RegOpBase(_machInst, mnem, _instMnem, 179 isMicro, isDelayed, isFirst, isLast, 180 _src1, _dest, _dataSize, _ext, 181 __opClass), 182 imm8(_imm8) 183 { 184 } 185 186 std::string generateDisassembly(Addr pc, 187 const SymbolTable *symtab) const; 188 }; 189} 190 191#endif //__ARCH_X86_INSTS_MICROREGOP_HH__ 192