faults.cc revision 7720:65d338a8dba4
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You may use the software subject to the license 105083Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 115083Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 125083Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 135083Sgblack@eecs.umich.edu * 145083Sgblack@eecs.umich.edu * Copyright (c) 2003-2007 The Regents of The University of Michigan 155083Sgblack@eecs.umich.edu * All rights reserved. 165083Sgblack@eecs.umich.edu * 175083Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 185083Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 195083Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 205083Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 215083Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 225083Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 235083Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 245083Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 255083Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 265083Sgblack@eecs.umich.edu * this software without specific prior written permission. 275083Sgblack@eecs.umich.edu * 285083Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295083Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305083Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315083Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325083Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335083Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345083Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355083Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365083Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375083Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385083Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395083Sgblack@eecs.umich.edu * 405083Sgblack@eecs.umich.edu * Authors: Gabe Black 415083Sgblack@eecs.umich.edu */ 425083Sgblack@eecs.umich.edu 435083Sgblack@eecs.umich.edu#include "arch/x86/decoder.hh" 445083Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 455083Sgblack@eecs.umich.edu#include "base/trace.hh" 465083Sgblack@eecs.umich.edu#include "config/full_system.hh" 475083Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 485083Sgblack@eecs.umich.edu#if !FULL_SYSTEM 495083Sgblack@eecs.umich.edu#include "arch/x86/isa_traits.hh" 505083Sgblack@eecs.umich.edu#include "mem/page_table.hh" 515083Sgblack@eecs.umich.edu#include "sim/process.hh" 525083Sgblack@eecs.umich.edu#else 535083Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 545083Sgblack@eecs.umich.edu#endif 555083Sgblack@eecs.umich.edu 565083Sgblack@eecs.umich.edunamespace X86ISA 575083Sgblack@eecs.umich.edu{ 585083Sgblack@eecs.umich.edu#if FULL_SYSTEM 595083Sgblack@eecs.umich.edu void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst) 605083Sgblack@eecs.umich.edu { 615083Sgblack@eecs.umich.edu PCState pcState = tc->pcState(); 625083Sgblack@eecs.umich.edu Addr pc = pcState.pc(); 635083Sgblack@eecs.umich.edu DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe()); 645083Sgblack@eecs.umich.edu using namespace X86ISAInst::RomLabels; 655083Sgblack@eecs.umich.edu HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 665083Sgblack@eecs.umich.edu MicroPC entry; 675083Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 685083Sgblack@eecs.umich.edu if (isSoft()) { 695083Sgblack@eecs.umich.edu entry = extern_label_longModeSoftInterrupt; 705083Sgblack@eecs.umich.edu } else { 715083Sgblack@eecs.umich.edu entry = extern_label_longModeInterrupt; 725083Sgblack@eecs.umich.edu } 735083Sgblack@eecs.umich.edu } else { 745083Sgblack@eecs.umich.edu entry = extern_label_legacyModeInterrupt; 755083Sgblack@eecs.umich.edu } 765083Sgblack@eecs.umich.edu tc->setIntReg(INTREG_MICRO(1), vector); 775083Sgblack@eecs.umich.edu tc->setIntReg(INTREG_MICRO(7), pc); 785083Sgblack@eecs.umich.edu if (errorCode != (uint64_t)(-1)) { 795083Sgblack@eecs.umich.edu if (m5reg.mode == LongMode) { 805083Sgblack@eecs.umich.edu entry = extern_label_longModeInterruptWithError; 815083Sgblack@eecs.umich.edu } else { 825083Sgblack@eecs.umich.edu panic("Legacy mode interrupts with error codes " 835083Sgblack@eecs.umich.edu "aren't implementde.\n"); 845083Sgblack@eecs.umich.edu } 855083Sgblack@eecs.umich.edu // Software interrupts shouldn't have error codes. If one does, 865083Sgblack@eecs.umich.edu // there would need to be microcode to set it up. 875083Sgblack@eecs.umich.edu assert(!isSoft()); 885083Sgblack@eecs.umich.edu tc->setIntReg(INTREG_MICRO(15), errorCode); 895083Sgblack@eecs.umich.edu } 905083Sgblack@eecs.umich.edu pcState.upc(romMicroPC(entry)); 915083Sgblack@eecs.umich.edu pcState.nupc(romMicroPC(entry) + 1); 925083Sgblack@eecs.umich.edu tc->pcState(pcState); 935083Sgblack@eecs.umich.edu } 945083Sgblack@eecs.umich.edu 955083Sgblack@eecs.umich.edu std::string 965083Sgblack@eecs.umich.edu X86FaultBase::describe() const 975083Sgblack@eecs.umich.edu { 985083Sgblack@eecs.umich.edu std::stringstream ss; 995083Sgblack@eecs.umich.edu ccprintf(ss, "%s", mnemonic()); 1005083Sgblack@eecs.umich.edu if (errorCode != (uint64_t)(-1)) { 1015083Sgblack@eecs.umich.edu ccprintf(ss, "(%#x)", errorCode); 1025083Sgblack@eecs.umich.edu } 1035083Sgblack@eecs.umich.edu 1045083Sgblack@eecs.umich.edu return ss.str(); 105 } 106 107 void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst) 108 { 109 X86FaultBase::invoke(tc); 110 // This is the same as a fault, but it happens -after- the instruction. 111 PCState pc = tc->pcState(); 112 pc.uEnd(); 113 } 114 115 void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst) 116 { 117 panic("Abort exception!"); 118 } 119 120 void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst) 121 { 122 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 123 X86FaultBase::invoke(tc); 124 /* 125 * If something bad happens while trying to enter the page fault 126 * handler, I'm pretty sure that's a double fault and then all bets are 127 * off. That means it should be safe to update this state now. 128 */ 129 if (m5reg.mode == LongMode) { 130 tc->setMiscReg(MISCREG_CR2, addr); 131 } else { 132 tc->setMiscReg(MISCREG_CR2, (uint32_t)addr); 133 } 134 } 135 136 std::string 137 PageFault::describe() const 138 { 139 std::stringstream ss; 140 ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr); 141 return ss.str(); 142 } 143 144 void 145 InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst) 146 { 147 DPRINTF(Faults, "Init interrupt.\n"); 148 // The otherwise unmodified integer registers should be set to 0. 149 for (int index = 0; index < NUM_INTREGS; index++) { 150 tc->setIntReg(index, 0); 151 } 152 153 CR0 cr0 = tc->readMiscReg(MISCREG_CR0); 154 CR0 newCR0 = 1 << 4; 155 newCR0.cd = cr0.cd; 156 newCR0.nw = cr0.nw; 157 tc->setMiscReg(MISCREG_CR0, newCR0); 158 tc->setMiscReg(MISCREG_CR2, 0); 159 tc->setMiscReg(MISCREG_CR3, 0); 160 tc->setMiscReg(MISCREG_CR4, 0); 161 162 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL); 163 164 tc->setMiscReg(MISCREG_EFER, 0); 165 166 SegAttr dataAttr = 0; 167 dataAttr.dpl = 0; 168 dataAttr.unusable = 0; 169 dataAttr.defaultSize = 0; 170 dataAttr.longMode = 0; 171 dataAttr.avl = 0; 172 dataAttr.granularity = 0; 173 dataAttr.present = 1; 174 dataAttr.type = 3; 175 dataAttr.writable = 1; 176 dataAttr.readable = 1; 177 dataAttr.expandDown = 0; 178 dataAttr.system = 1; 179 180 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) { 181 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0); 182 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0); 183 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0); 184 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff); 185 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr); 186 } 187 188 SegAttr codeAttr = 0; 189 codeAttr.dpl = 0; 190 codeAttr.unusable = 0; 191 codeAttr.defaultSize = 0; 192 codeAttr.longMode = 0; 193 codeAttr.avl = 0; 194 codeAttr.granularity = 0; 195 codeAttr.present = 1; 196 codeAttr.type = 10; 197 codeAttr.writable = 0; 198 codeAttr.readable = 1; 199 codeAttr.expandDown = 0; 200 codeAttr.system = 1; 201 202 tc->setMiscReg(MISCREG_CS, 0xf000); 203 tc->setMiscReg(MISCREG_CS_BASE, 204 0x00000000ffff0000ULL); 205 tc->setMiscReg(MISCREG_CS_EFF_BASE, 206 0x00000000ffff0000ULL); 207 // This has the base value pre-added. 208 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff); 209 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr); 210 211 PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE)); 212 tc->pcState(pc); 213 214 tc->setMiscReg(MISCREG_TSG_BASE, 0); 215 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff); 216 217 tc->setMiscReg(MISCREG_IDTR_BASE, 0); 218 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 219 220 tc->setMiscReg(MISCREG_TSL, 0); 221 tc->setMiscReg(MISCREG_TSL_BASE, 0); 222 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff); 223 tc->setMiscReg(MISCREG_TSL_ATTR, 0); 224 225 tc->setMiscReg(MISCREG_TR, 0); 226 tc->setMiscReg(MISCREG_TR_BASE, 0); 227 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); 228 tc->setMiscReg(MISCREG_TR_ATTR, 0); 229 230 // This value should be the family/model/stepping of the processor. 231 // (page 418). It should be consistent with the value from CPUID, but 232 // the actual value probably doesn't matter much. 233 tc->setIntReg(INTREG_RDX, 0); 234 235 tc->setMiscReg(MISCREG_DR0, 0); 236 tc->setMiscReg(MISCREG_DR1, 0); 237 tc->setMiscReg(MISCREG_DR2, 0); 238 tc->setMiscReg(MISCREG_DR3, 0); 239 240 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL); 241 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL); 242 243 // Update the handy M5 Reg. 244 tc->setMiscReg(MISCREG_M5_REG, 0); 245 MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt; 246 pc.upc(romMicroPC(entry)); 247 pc.nupc(romMicroPC(entry) + 1); 248 tc->pcState(pc); 249 } 250 251 void 252 StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst) 253 { 254 DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector); 255 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG); 256 if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) { 257 panic("Startup IPI recived outside of real mode. " 258 "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode); 259 } 260 261 tc->setMiscReg(MISCREG_CS, vector << 8); 262 tc->setMiscReg(MISCREG_CS_BASE, vector << 12); 263 tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12); 264 // This has the base value pre-added. 265 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff); 266 267 tc->pcState(tc->readMiscReg(MISCREG_CS_BASE)); 268 } 269 270#else 271 272 void 273 InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst) 274 { 275 panic("Unrecognized/invalid instruction executed:\n %s", 276 inst->machInst); 277 } 278 279 void 280 PageFault::invoke(ThreadContext * tc, StaticInstPtr inst) 281 { 282 PageFaultErrorCode code = errorCode; 283 const char *modeStr = ""; 284 if (code.fetch) 285 modeStr = "execute"; 286 else if (code.write) 287 modeStr = "write"; 288 else 289 modeStr = "read"; 290 panic("Tried to %s unmapped address %#x.\n", modeStr, addr); 291 } 292 293#endif 294} // namespace X86ISA 295 296