faults.cc revision 7720 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2007 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/x86/decoder.hh"
44#include "arch/x86/faults.hh"
45#include "base/trace.hh"
46#include "config/full_system.hh"
47#include "cpu/thread_context.hh"
48#if !FULL_SYSTEM
49#include "arch/x86/isa_traits.hh"
50#include "mem/page_table.hh"
51#include "sim/process.hh"
52#else
53#include "arch/x86/tlb.hh"
54#endif
55
56namespace X86ISA
57{
58#if FULL_SYSTEM
59    void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
60    {
61        PCState pcState = tc->pcState();
62        Addr pc = pcState.pc();
63        DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
64        using namespace X86ISAInst::RomLabels;
65        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
66        MicroPC entry;
67        if (m5reg.mode == LongMode) {
68            if (isSoft()) {
69                entry = extern_label_longModeSoftInterrupt;
70            } else {
71                entry = extern_label_longModeInterrupt;
72            }
73        } else {
74            entry = extern_label_legacyModeInterrupt;
75        }
76        tc->setIntReg(INTREG_MICRO(1), vector);
77        tc->setIntReg(INTREG_MICRO(7), pc);
78        if (errorCode != (uint64_t)(-1)) {
79            if (m5reg.mode == LongMode) {
80                entry = extern_label_longModeInterruptWithError;
81            } else {
82                panic("Legacy mode interrupts with error codes "
83                        "aren't implementde.\n");
84            }
85            // Software interrupts shouldn't have error codes. If one does,
86            // there would need to be microcode to set it up.
87            assert(!isSoft());
88            tc->setIntReg(INTREG_MICRO(15), errorCode);
89        }
90        pcState.upc(romMicroPC(entry));
91        pcState.nupc(romMicroPC(entry) + 1);
92        tc->pcState(pcState);
93    }
94
95    std::string
96    X86FaultBase::describe() const
97    {
98        std::stringstream ss;
99        ccprintf(ss, "%s", mnemonic());
100        if (errorCode != (uint64_t)(-1)) {
101            ccprintf(ss, "(%#x)", errorCode);
102        }
103
104        return ss.str();
105    }
106
107    void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
108    {
109        X86FaultBase::invoke(tc);
110        // This is the same as a fault, but it happens -after- the instruction.
111        PCState pc = tc->pcState();
112        pc.uEnd();
113    }
114
115    void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
116    {
117        panic("Abort exception!");
118    }
119
120    void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
121    {
122        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
123        X86FaultBase::invoke(tc);
124        /*
125         * If something bad happens while trying to enter the page fault
126         * handler, I'm pretty sure that's a double fault and then all bets are
127         * off. That means it should be safe to update this state now.
128         */
129        if (m5reg.mode == LongMode) {
130            tc->setMiscReg(MISCREG_CR2, addr);
131        } else {
132            tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
133        }
134    }
135
136    std::string
137    PageFault::describe() const
138    {
139        std::stringstream ss;
140        ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
141        return ss.str();
142    }
143
144    void
145    InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
146    {
147        DPRINTF(Faults, "Init interrupt.\n");
148        // The otherwise unmodified integer registers should be set to 0.
149        for (int index = 0; index < NUM_INTREGS; index++) {
150            tc->setIntReg(index, 0);
151        }
152
153        CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
154        CR0 newCR0 = 1 << 4;
155        newCR0.cd = cr0.cd;
156        newCR0.nw = cr0.nw;
157        tc->setMiscReg(MISCREG_CR0, newCR0);
158        tc->setMiscReg(MISCREG_CR2, 0);
159        tc->setMiscReg(MISCREG_CR3, 0);
160        tc->setMiscReg(MISCREG_CR4, 0);
161
162        tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
163
164        tc->setMiscReg(MISCREG_EFER, 0);
165
166        SegAttr dataAttr = 0;
167        dataAttr.dpl = 0;
168        dataAttr.unusable = 0;
169        dataAttr.defaultSize = 0;
170        dataAttr.longMode = 0;
171        dataAttr.avl = 0;
172        dataAttr.granularity = 0;
173        dataAttr.present = 1;
174        dataAttr.type = 3;
175        dataAttr.writable = 1;
176        dataAttr.readable = 1;
177        dataAttr.expandDown = 0;
178        dataAttr.system = 1;
179
180        for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
181            tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
182            tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
183            tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
184            tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
185            tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
186        }
187
188        SegAttr codeAttr = 0;
189        codeAttr.dpl = 0;
190        codeAttr.unusable = 0;
191        codeAttr.defaultSize = 0;
192        codeAttr.longMode = 0;
193        codeAttr.avl = 0;
194        codeAttr.granularity = 0;
195        codeAttr.present = 1;
196        codeAttr.type = 10;
197        codeAttr.writable = 0;
198        codeAttr.readable = 1;
199        codeAttr.expandDown = 0;
200        codeAttr.system = 1;
201
202        tc->setMiscReg(MISCREG_CS, 0xf000);
203        tc->setMiscReg(MISCREG_CS_BASE,
204                0x00000000ffff0000ULL);
205        tc->setMiscReg(MISCREG_CS_EFF_BASE,
206                0x00000000ffff0000ULL);
207        // This has the base value pre-added.
208        tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
209        tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
210
211        PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
212        tc->pcState(pc);
213
214        tc->setMiscReg(MISCREG_TSG_BASE, 0);
215        tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
216
217        tc->setMiscReg(MISCREG_IDTR_BASE, 0);
218        tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
219
220        tc->setMiscReg(MISCREG_TSL, 0);
221        tc->setMiscReg(MISCREG_TSL_BASE, 0);
222        tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
223        tc->setMiscReg(MISCREG_TSL_ATTR, 0);
224
225        tc->setMiscReg(MISCREG_TR, 0);
226        tc->setMiscReg(MISCREG_TR_BASE, 0);
227        tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
228        tc->setMiscReg(MISCREG_TR_ATTR, 0);
229
230        // This value should be the family/model/stepping of the processor.
231        // (page 418). It should be consistent with the value from CPUID, but
232        // the actual value probably doesn't matter much.
233        tc->setIntReg(INTREG_RDX, 0);
234
235        tc->setMiscReg(MISCREG_DR0, 0);
236        tc->setMiscReg(MISCREG_DR1, 0);
237        tc->setMiscReg(MISCREG_DR2, 0);
238        tc->setMiscReg(MISCREG_DR3, 0);
239
240        tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
241        tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
242
243        // Update the handy M5 Reg.
244        tc->setMiscReg(MISCREG_M5_REG, 0);
245        MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
246        pc.upc(romMicroPC(entry));
247        pc.nupc(romMicroPC(entry) + 1);
248        tc->pcState(pc);
249    }
250
251    void
252    StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
253    {
254        DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
255        HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
256        if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
257            panic("Startup IPI recived outside of real mode. "
258                    "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
259        }
260
261        tc->setMiscReg(MISCREG_CS, vector << 8);
262        tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
263        tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
264        // This has the base value pre-added.
265        tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
266
267        tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
268    }
269
270#else
271
272    void
273    InvalidOpcode::invoke(ThreadContext * tc, StaticInstPtr inst)
274    {
275        panic("Unrecognized/invalid instruction executed:\n %s",
276                inst->machInst);
277    }
278
279    void
280    PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
281    {
282        PageFaultErrorCode code = errorCode;
283        const char *modeStr = "";
284        if (code.fetch)
285            modeStr = "execute";
286        else if (code.write)
287            modeStr = "write";
288        else
289            modeStr = "read";
290        panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
291    }
292
293#endif
294} // namespace X86ISA
295
296