faults.cc revision 11320 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2007 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include "arch/x86/generated/decoder.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/isa_traits.hh"
46#include "base/trace.hh"
47#include "cpu/thread_context.hh"
48#include "debug/Faults.hh"
49#include "sim/full_system.hh"
50
51namespace X86ISA
52{
53    void X86FaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
54    {
55        if (!FullSystem) {
56            FaultBase::invoke(tc, inst);
57            return;
58        }
59
60        PCState pcState = tc->pcState();
61        Addr pc = pcState.pc();
62        DPRINTF(Faults, "RIP %#x: vector %d: %s\n",
63                pc, vector, describe());
64        using namespace X86ISAInst::RomLabels;
65        HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
66        MicroPC entry;
67        if (m5reg.mode == LongMode) {
68            if (isSoft()) {
69                entry = extern_label_longModeSoftInterrupt;
70            } else {
71                entry = extern_label_longModeInterrupt;
72            }
73        } else {
74            entry = extern_label_legacyModeInterrupt;
75        }
76        tc->setIntReg(INTREG_MICRO(1), vector);
77        tc->setIntReg(INTREG_MICRO(7), pc);
78        if (errorCode != (uint64_t)(-1)) {
79            if (m5reg.mode == LongMode) {
80                entry = extern_label_longModeInterruptWithError;
81            } else {
82                panic("Legacy mode interrupts with error codes "
83                        "aren't implementde.\n");
84            }
85            // Software interrupts shouldn't have error codes. If one
86            // does, there would need to be microcode to set it up.
87            assert(!isSoft());
88            tc->setIntReg(INTREG_MICRO(15), errorCode);
89        }
90        pcState.upc(romMicroPC(entry));
91        pcState.nupc(romMicroPC(entry) + 1);
92        tc->pcState(pcState);
93    }
94
95    std::string
96    X86FaultBase::describe() const
97    {
98        std::stringstream ss;
99        ccprintf(ss, "%s", mnemonic());
100        if (errorCode != (uint64_t)(-1)) {
101            ccprintf(ss, "(%#x)", errorCode);
102        }
103
104        return ss.str();
105    }
106
107    void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst)
108    {
109        X86FaultBase::invoke(tc);
110        if (!FullSystem)
111            return;
112
113        // This is the same as a fault, but it happens -after- the
114        // instruction.
115        PCState pc = tc->pcState();
116        pc.uEnd();
117    }
118
119    void X86Abort::invoke(ThreadContext * tc, const StaticInstPtr &inst)
120    {
121        panic("Abort exception!");
122    }
123
124    void
125    InvalidOpcode::invoke(ThreadContext * tc, const StaticInstPtr &inst)
126    {
127        if (FullSystem) {
128            X86Fault::invoke(tc, inst);
129        } else {
130            panic("Unrecognized/invalid instruction executed:\n %s",
131                    inst->machInst);
132        }
133    }
134
135    void PageFault::invoke(ThreadContext * tc, const StaticInstPtr &inst)
136    {
137        if (FullSystem) {
138            /* Invalidate any matching TLB entries before handling the page fault */
139            tc->getITBPtr()->demapPage(addr, 0);
140            tc->getDTBPtr()->demapPage(addr, 0);
141            HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
142            X86FaultBase::invoke(tc);
143            /*
144             * If something bad happens while trying to enter the page fault
145             * handler, I'm pretty sure that's a double fault and then all
146             * bets are off. That means it should be safe to update this
147             * state now.
148             */
149            if (m5reg.mode == LongMode) {
150                tc->setMiscReg(MISCREG_CR2, addr);
151            } else {
152                tc->setMiscReg(MISCREG_CR2, (uint32_t)addr);
153            }
154        } else {
155            PageFaultErrorCode code = errorCode;
156            const char *modeStr = "";
157            if (code.fetch)
158                modeStr = "execute";
159            else if (code.write)
160                modeStr = "write";
161            else
162                modeStr = "read";
163            panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
164        }
165    }
166
167    std::string
168    PageFault::describe() const
169    {
170        std::stringstream ss;
171        ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr);
172        return ss.str();
173    }
174
175    void
176    InitInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
177    {
178        DPRINTF(Faults, "Init interrupt.\n");
179        // The otherwise unmodified integer registers should be set to 0.
180        for (int index = 0; index < NUM_INTREGS; index++) {
181            tc->setIntReg(index, 0);
182        }
183
184        CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
185        CR0 newCR0 = 1 << 4;
186        newCR0.cd = cr0.cd;
187        newCR0.nw = cr0.nw;
188        tc->setMiscReg(MISCREG_CR0, newCR0);
189        tc->setMiscReg(MISCREG_CR2, 0);
190        tc->setMiscReg(MISCREG_CR3, 0);
191        tc->setMiscReg(MISCREG_CR4, 0);
192
193        tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
194
195        tc->setMiscReg(MISCREG_EFER, 0);
196
197        SegAttr dataAttr = 0;
198        dataAttr.dpl = 0;
199        dataAttr.unusable = 0;
200        dataAttr.defaultSize = 0;
201        dataAttr.longMode = 0;
202        dataAttr.avl = 0;
203        dataAttr.granularity = 0;
204        dataAttr.present = 1;
205        dataAttr.type = 3;
206        dataAttr.writable = 1;
207        dataAttr.readable = 1;
208        dataAttr.expandDown = 0;
209        dataAttr.system = 1;
210
211        for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
212            tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
213            tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
214            tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
215            tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
216            tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
217        }
218
219        SegAttr codeAttr = 0;
220        codeAttr.dpl = 0;
221        codeAttr.unusable = 0;
222        codeAttr.defaultSize = 0;
223        codeAttr.longMode = 0;
224        codeAttr.avl = 0;
225        codeAttr.granularity = 0;
226        codeAttr.present = 1;
227        codeAttr.type = 10;
228        codeAttr.writable = 0;
229        codeAttr.readable = 1;
230        codeAttr.expandDown = 0;
231        codeAttr.system = 1;
232
233        tc->setMiscReg(MISCREG_CS, 0xf000);
234        tc->setMiscReg(MISCREG_CS_BASE,
235                0x00000000ffff0000ULL);
236        tc->setMiscReg(MISCREG_CS_EFF_BASE,
237                0x00000000ffff0000ULL);
238        // This has the base value pre-added.
239        tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
240        tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
241
242        PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
243        tc->pcState(pc);
244
245        tc->setMiscReg(MISCREG_TSG_BASE, 0);
246        tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
247
248        tc->setMiscReg(MISCREG_IDTR_BASE, 0);
249        tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
250
251        SegAttr tslAttr = 0;
252        tslAttr.present = 1;
253        tslAttr.type = 2; // LDT
254        tc->setMiscReg(MISCREG_TSL, 0);
255        tc->setMiscReg(MISCREG_TSL_BASE, 0);
256        tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
257        tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
258
259        SegAttr trAttr = 0;
260        trAttr.present = 1;
261        trAttr.type = 3; // Busy 16-bit TSS
262        tc->setMiscReg(MISCREG_TR, 0);
263        tc->setMiscReg(MISCREG_TR_BASE, 0);
264        tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
265        tc->setMiscReg(MISCREG_TR_ATTR, trAttr);
266
267        // This value should be the family/model/stepping of the processor.
268        // (page 418). It should be consistent with the value from CPUID, but
269        // the actual value probably doesn't matter much.
270        tc->setIntReg(INTREG_RDX, 0);
271
272        tc->setMiscReg(MISCREG_DR0, 0);
273        tc->setMiscReg(MISCREG_DR1, 0);
274        tc->setMiscReg(MISCREG_DR2, 0);
275        tc->setMiscReg(MISCREG_DR3, 0);
276
277        tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
278        tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
279
280        tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
281
282        // Flag all elements on the x87 stack as empty.
283        tc->setMiscReg(MISCREG_FTW, 0xFFFF);
284
285        // Update the handy M5 Reg.
286        tc->setMiscReg(MISCREG_M5_REG, 0);
287        MicroPC entry = X86ISAInst::RomLabels::extern_label_initIntHalt;
288        pc.upc(romMicroPC(entry));
289        pc.nupc(romMicroPC(entry) + 1);
290        tc->pcState(pc);
291    }
292
293    void
294    StartupInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
295    {
296        DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
297        HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
298        if (m5Reg.mode != LegacyMode || m5Reg.submode != RealMode) {
299            panic("Startup IPI recived outside of real mode. "
300                    "Don't know what to do. %d, %d", m5Reg.mode, m5Reg.submode);
301        }
302
303        tc->setMiscReg(MISCREG_CS, vector << 8);
304        tc->setMiscReg(MISCREG_CS_BASE, vector << 12);
305        tc->setMiscReg(MISCREG_CS_EFF_BASE, vector << 12);
306        // This has the base value pre-added.
307        tc->setMiscReg(MISCREG_CS_LIMIT, 0xffff);
308
309        tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
310    }
311} // namespace X86ISA
312
313