cpuid.cc revision 6040:818914aeebc1
1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/x86/cpuid.hh" 32#include "base/bitfield.hh" 33#include "cpu/thread_context.hh" 34 35namespace X86ISA { 36 enum StandardCpuidFunction { 37 VendorAndLargestStdFunc, 38 FamilyModelStepping, 39 NumStandardCpuidFuncs 40 }; 41 42 enum ExtendedCpuidFunctions { 43 VendorAndLargestExtFunc, 44 FamilyModelSteppingBrandFeatures, 45 NameString1, 46 NameString2, 47 NameString3, 48 L1CacheAndTLB, 49 L2L3CacheAndL2TLB, 50 APMInfo, 51 52 /* 53 * The following are defined by the spec but not yet implemented 54 */ 55/* LongModeAddressSize, 56 // Function 9 is reserved 57 SVMInfo = 10, 58 // Functions 11-24 are reserved 59 TLB1GBPageInfo = 25, 60 PerformanceInfo,*/ 61 62 NumExtendedCpuidFuncs 63 }; 64 65 static const int vendorStringSize = 13; 66 static const char vendorString[vendorStringSize] = "M5 Simulator"; 67 static const int nameStringSize = 48; 68 static const char nameString[nameStringSize] = "Fake M5 x86_64 CPU"; 69 70 uint64_t 71 stringToRegister(const char *str) 72 { 73 uint64_t reg = 0; 74 for (int pos = 3; pos >=0; pos--) { 75 reg <<= 8; 76 reg |= str[pos]; 77 } 78 return reg; 79 } 80 81 bool 82 doCpuid(ThreadContext * tc, uint32_t function, CpuidResult &result) 83 { 84 uint16_t family = bits(function, 31, 16); 85 uint16_t funcNum = bits(function, 15, 0); 86 if (family == 0x8000) { 87 // The extended functions 88 switch (funcNum) { 89 case VendorAndLargestExtFunc: 90 assert(vendorStringSize >= 12); 91 result = CpuidResult( 92 NumExtendedCpuidFuncs - 1, 93 stringToRegister(vendorString), 94 stringToRegister(vendorString + 4), 95 stringToRegister(vendorString + 8)); 96 break; 97 case FamilyModelSteppingBrandFeatures: 98 result = CpuidResult(0x00020f51, 0x00000405, 99 0xe3d3fbff, 0x00000001); 100 break; 101 case NameString1: 102 case NameString2: 103 case NameString3: 104 { 105 // Zero fill anything beyond the end of the string. This 106 // should go away once the string is a vetted parameter. 107 char cleanName[nameStringSize]; 108 memset(cleanName, '\0', nameStringSize); 109 strncpy(cleanName, nameString, nameStringSize); 110 111 int offset = (funcNum - NameString1) * 16; 112 assert(nameStringSize >= offset + 16); 113 result = CpuidResult( 114 stringToRegister(cleanName + offset + 0), 115 stringToRegister(cleanName + offset + 4), 116 stringToRegister(cleanName + offset + 8), 117 stringToRegister(cleanName + offset + 12)); 118 } 119 break; 120 case L1CacheAndTLB: 121 result = CpuidResult(0xff08ff08, 0xff20ff20, 122 0x40020140, 0x40020140); 123 break; 124 case L2L3CacheAndL2TLB: 125 result = CpuidResult(0x00000000, 0x42004200, 126 0x00000000, 0x04008140); 127 break; 128 case APMInfo: 129 result = CpuidResult(0x80000018, 0x68747541, 130 0x69746e65, 0x444d4163); 131 break; 132/* case LongModeAddressSize: 133 case SVMInfo: 134 case TLB1GBPageInfo: 135 case PerformanceInfo:*/ 136 default: 137 return false; 138 } 139 } else if(family == 0x0000) { 140 // The standard functions 141 switch (funcNum) { 142 case VendorAndLargestStdFunc: 143 assert(vendorStringSize >= 12); 144 result = CpuidResult( 145 NumStandardCpuidFuncs - 1, 146 stringToRegister(vendorString), 147 stringToRegister(vendorString + 4), 148 stringToRegister(vendorString + 8)); 149 break; 150 case FamilyModelStepping: 151 result = CpuidResult(0x00020f51, 0000000405, 152 0xe3d3fbff, 0x00000001); 153 break; 154 default: 155 return false; 156 } 157 } 158 return true; 159 } 160} //namespace X86ISA 161