intelmp.hh revision 7087:fb8d5786ff30 
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_BIOS_INTELMP_HH__
41#define __ARCH_X86_BIOS_INTELMP_HH__
42
43#include <string>
44#include <vector>
45
46#include "base/bitfield.hh"
47#include "sim/sim_object.hh"
48
49#include "enums/X86IntelMPAddressType.hh"
50#include "enums/X86IntelMPInterruptType.hh"
51#include "enums/X86IntelMPPolarity.hh"
52#include "enums/X86IntelMPRangeList.hh"
53#include "enums/X86IntelMPTriggerMode.hh"
54
55class FunctionalPort;
56
57// Config entry types
58class X86IntelMPBaseConfigEntryParams;
59class X86IntelMPExtConfigEntryParams;
60
61// General table structures
62class X86IntelMPConfigTableParams;
63class X86IntelMPFloatingPointerParams;
64
65// Base entry types
66class X86IntelMPBusParams;
67class X86IntelMPIOAPICParams;
68class X86IntelMPIOIntAssignmentParams;
69class X86IntelMPLocalIntAssignmentParams;
70class X86IntelMPProcessorParams;
71
72// Extended entry types
73class X86IntelMPAddrSpaceMappingParams;
74class X86IntelMPBusHierarchyParams;
75class X86IntelMPCompatAddrSpaceModParams;
76
77namespace X86ISA
78{
79
80namespace IntelMP
81{
82
83class FloatingPointer : public SimObject
84{
85  protected:
86    typedef X86IntelMPFloatingPointerParams Params;
87
88    uint32_t tableAddr;
89    uint8_t specRev;
90    uint8_t defaultConfig;
91    bool imcrPresent;
92
93    static const char signature[];
94
95  public:
96
97    Addr writeOut(FunctionalPort * port, Addr addr);
98
99    Addr getTableAddr()
100    {
101        return tableAddr;
102    }
103
104    void setTableAddr(Addr addr)
105    {
106        tableAddr = addr;
107    }
108
109    FloatingPointer(Params * p);
110};
111
112class BaseConfigEntry : public SimObject
113{
114  protected:
115    typedef X86IntelMPBaseConfigEntryParams Params;
116
117    uint8_t type;
118
119  public:
120
121    virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
122
123    BaseConfigEntry(Params * p, uint8_t _type);
124};
125
126class ExtConfigEntry : public SimObject
127{
128  protected:
129    typedef X86IntelMPExtConfigEntryParams Params;
130
131    uint8_t type;
132    uint8_t length;
133
134  public:
135
136    virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
137
138    ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length);
139};
140
141class ConfigTable : public SimObject
142{
143  protected:
144    typedef X86IntelMPConfigTableParams Params;
145
146    static const char signature[];
147
148    uint8_t specRev;
149    std::string oemID;
150    std::string productID;
151    uint32_t oemTableAddr;
152    uint16_t oemTableSize;
153    uint32_t localApic;
154
155    std::vector<BaseConfigEntry *> baseEntries;
156    std::vector<ExtConfigEntry *> extEntries;
157
158  public:
159    Addr writeOut(FunctionalPort * port, Addr addr);
160
161    ConfigTable(Params * p);
162};
163
164class Processor : public BaseConfigEntry
165{
166  protected:
167    typedef X86IntelMPProcessorParams Params;
168
169    uint8_t localApicID;
170    uint8_t localApicVersion;
171    uint8_t cpuFlags;
172    uint32_t cpuSignature;
173    uint32_t featureFlags;
174
175  public:
176    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
177
178    Processor(Params * p);
179};
180
181class Bus : public BaseConfigEntry
182{
183  protected:
184    typedef X86IntelMPBusParams Params;
185
186    uint8_t busID;
187    std::string busType;
188
189  public:
190    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
191
192    Bus(Params * p);
193};
194
195class IOAPIC : public BaseConfigEntry
196{
197  protected:
198    typedef X86IntelMPIOAPICParams Params;
199
200    uint8_t id;
201    uint8_t version;
202    uint8_t flags;
203    uint32_t address;
204
205  public:
206    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
207
208    IOAPIC(Params * p);
209};
210
211class IntAssignment : public BaseConfigEntry
212{
213  protected:
214    uint8_t interruptType;
215
216    uint16_t flags;
217
218    uint8_t sourceBusID;
219    uint8_t sourceBusIRQ;
220
221    uint8_t destApicID;
222    uint8_t destApicIntIn;
223
224  public:
225    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
226
227    IntAssignment(X86IntelMPBaseConfigEntryParams * p,
228            Enums::X86IntelMPInterruptType _interruptType,
229            Enums::X86IntelMPPolarity polarity,
230            Enums::X86IntelMPTriggerMode trigger,
231            uint8_t _type,
232            uint8_t _sourceBusID, uint8_t _sourceBusIRQ,
233            uint8_t _destApicID, uint8_t _destApicIntIn) :
234        BaseConfigEntry(p, _type),
235        interruptType(_interruptType), flags(0),
236        sourceBusID(_sourceBusID), sourceBusIRQ(_sourceBusIRQ),
237        destApicID(_destApicID), destApicIntIn(_destApicIntIn)
238    {
239        replaceBits(flags, 0, 1, polarity);
240        replaceBits(flags, 2, 3, trigger);
241    }
242};
243
244class IOIntAssignment : public IntAssignment
245{
246  protected:
247    typedef X86IntelMPIOIntAssignmentParams Params;
248
249  public:
250    IOIntAssignment(Params * p);
251};
252
253class LocalIntAssignment : public IntAssignment
254{
255  protected:
256    typedef X86IntelMPLocalIntAssignmentParams Params;
257
258  public:
259    LocalIntAssignment(Params * p);
260};
261
262class AddrSpaceMapping : public ExtConfigEntry
263{
264  protected:
265    typedef X86IntelMPAddrSpaceMappingParams Params;
266
267    uint8_t busID;
268    uint8_t addrType;
269    uint64_t addr;
270    uint64_t addrLength;
271
272  public:
273    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
274
275    AddrSpaceMapping(Params * p);
276};
277
278class BusHierarchy : public ExtConfigEntry
279{
280  protected:
281    typedef X86IntelMPBusHierarchyParams Params;
282
283    uint8_t busID;
284    uint8_t info;
285    uint8_t parentBus;
286
287  public:
288    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
289
290    BusHierarchy(Params * p);
291};
292
293class CompatAddrSpaceMod : public ExtConfigEntry
294{
295  protected:
296    typedef X86IntelMPCompatAddrSpaceModParams Params;
297
298    uint8_t busID;
299    uint8_t mod;
300    uint32_t rangeList;
301
302  public:
303    Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
304
305    CompatAddrSpaceMod(Params * p);
306};
307
308} //IntelMP
309
310} //X86ISA
311
312#endif
313