xref: /gem5/src/arch/x86/X86TLB.py

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# Authors: Gabe Black

from m5.params import *
from m5.proxy import *

from BaseTLB import BaseTLB
from MemObject import MemObject

class X86PagetableWalker(MemObject):
    type = 'X86PagetableWalker'
    cxx_class = 'X86ISA::Walker'
    cxx_header = 'arch/x86/pagetable_walker.hh'
    port = MasterPort("Port for the hardware table walker")
    system = Param.System(Parent.any, "system object")
    num_squash_per_cycle = Param.Unsigned(4,
            "Number of outstanding walks that can be squashed per cycle")

class X86TLB(BaseTLB):
    type = 'X86TLB'
    cxx_class = 'X86ISA::TLB'
    cxx_header = 'arch/x86/tlb.hh'
    size = Param.Int(64, "TLB size")
    walker = Param.X86PagetableWalker(\
            X86PagetableWalker(), "page table walker")