X86TLB.py revision 9338 
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33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Gabe Black
37
38from m5.params import *
39from m5.proxy import *
40
41from BaseTLB import BaseTLB
42from MemObject import MemObject
43
44class X86PagetableWalker(MemObject):
45    type = 'X86PagetableWalker'
46    cxx_class = 'X86ISA::Walker'
47    cxx_header = 'arch/x86/pagetable_walker.hh'
48    port = MasterPort("Port for the hardware table walker")
49    system = Param.System(Parent.any, "system object")
50
51class X86TLB(BaseTLB):
52    type = 'X86TLB'
53    cxx_class = 'X86ISA::TLB'
54    cxx_header = 'arch/x86/tlb.hh'
55    size = Param.Int(64, "TLB size")
56    walker = Param.X86PagetableWalker(\
57            X86PagetableWalker(), "page table walker")
58