vtophys.cc revision 8229:78bf55f23338 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <string>
32
33#include "arch/sparc/tlb.hh"
34#include "arch/sparc/vtophys.hh"
35#include "base/chunk_generator.hh"
36#include "base/compiler.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "mem/vport.hh"
40
41using namespace std;
42
43namespace SparcISA {
44
45Addr
46vtophys(Addr vaddr)
47{
48    // In SPARC it's almost always impossible to turn a VA->PA w/o a
49    // context The only times we can kinda do it are if we have a
50    // SegKPM mapping and can find the real address in the tlb or we
51    // have a physical adddress already (beacuse we are looking at the
52    // hypervisor) Either case is rare, so we'll just panic.
53
54    panic("vtophys() without context on SPARC largly worthless\n");
55    M5_DUMMY_RETURN;
56}
57
58Addr
59vtophys(ThreadContext *tc, Addr addr)
60{
61    // Here we have many options and are really implementing something like
62    // a fill handler to find the address since there isn't a multilevel
63    // table for us to walk around.
64    //
65    // 1. We are currently hyperpriv, return the address unmodified
66    // 2. The mmu is off return(ra->pa)
67    // 3. We are currently priv, use ctx0* tsbs to find the page
68    // 4. We are not priv, use ctxN0* tsbs to find the page
69    // For all accesses we check the tlbs first since it's possible that
70    // long standing pages (e.g. locked kernel mappings) won't be in the tsb
71    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
72
73    bool hpriv = bits(tlbdata,0,0);
74    // bool priv = bits(tlbdata,2,2);
75    bool addr_mask = bits(tlbdata,3,3);
76    bool data_real = !bits(tlbdata,5,5);
77    bool inst_real = !bits(tlbdata,4,4);
78    bool ctx_zero  = bits(tlbdata,18,16) > 0;
79    int part_id = bits(tlbdata,15,8);
80    int pri_context = bits(tlbdata,47,32);
81    // int sec_context = bits(tlbdata,63,48);
82
83    FunctionalPort *mem = tc->getPhysPort();
84    TLB* itb = tc->getITBPtr();
85    TLB* dtb = tc->getDTBPtr();
86    TlbEntry* tbe;
87    PageTableEntry pte;
88    Addr tsbs[4];
89    Addr va_tag;
90    TteTag ttetag;
91
92    if (hpriv)
93        return addr;
94
95    if (addr_mask)
96        addr = addr & VAddrAMask;
97
98    tbe = dtb->lookup(addr, part_id, data_real, ctx_zero ? 0 : pri_context ,
99                      false);
100    if (tbe)
101        goto foundtbe;
102
103    tbe = itb->lookup(addr, part_id, inst_real, ctx_zero ? 0 : pri_context,
104                      false);
105    if (tbe)
106        goto foundtbe;
107
108    // We didn't find it in the tlbs, so lets look at the TSBs
109    dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs);
110    va_tag = bits(addr, 63, 22);
111    for (int x = 0; x < 4; x++) {
112        ttetag = betoh(mem->read<uint64_t>(tsbs[x]));
113        if (ttetag.valid() && ttetag.va() == va_tag) {
114            uint64_t entry = mem->read<uint64_t>(tsbs[x]) + sizeof(uint64_t);
115            // I think it's sun4v at least!
116            pte.populate(betoh(entry), PageTableEntry::sun4v);
117            DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TTE\n",
118                    addr, pte.translate(addr));
119            goto foundpte;
120        }
121    }
122    panic("couldn't translate %#x\n", addr);
123
124  foundtbe:
125    pte = tbe->pte;
126    DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr,
127            pte.translate(addr));
128  foundpte:
129    return pte.translate(addr);
130}
131
132} // namespace SparcISA
133