utility.hh revision 7627:3b0c4b819651
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_SPARC_UTILITY_HH__ 32#define __ARCH_SPARC_UTILITY_HH__ 33 34#include "arch/sparc/faults.hh" 35#include "arch/sparc/isa_traits.hh" 36#include "arch/sparc/registers.hh" 37#include "arch/sparc/tlb.hh" 38#include "base/misc.hh" 39#include "base/bitfield.hh" 40#include "cpu/thread_context.hh" 41 42namespace SparcISA 43{ 44 uint64_t getArgument(ThreadContext *tc, int number, bool fp); 45 46 static inline bool 47 inUserMode(ThreadContext *tc) 48 { 49 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) || 50 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2))); 51 } 52 53 /** 54 * Function to insure ISA semantics about 0 registers. 55 * @param tc The thread context. 56 */ 57 template <class TC> 58 void zeroRegisters(TC *tc); 59 60 inline void 61 initCPU(ThreadContext *tc, int cpuId) 62 { 63 static Fault por = new PowerOnReset(); 64 if (cpuId == 0) 65 por->invoke(tc); 66 67 } 68 69 inline void 70 startupCPU(ThreadContext *tc, int cpuId) 71 { 72#if FULL_SYSTEM 73 // Other CPUs will get activated by IPIs 74 if (cpuId == 0) 75 tc->activate(0); 76#else 77 tc->activate(0); 78#endif 79 } 80 81 void copyRegs(ThreadContext *src, ThreadContext *dest); 82 83 void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 84 85} // namespace SparcISA 86 87#endif 88