utility.hh revision 7572 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/registers.hh"
37#include "arch/sparc/tlb.hh"
38#include "base/misc.hh"
39#include "base/bitfield.hh"
40#include "cpu/thread_context.hh"
41
42namespace SparcISA
43{
44    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
45
46    static inline bool
47    inUserMode(ThreadContext *tc)
48    {
49        return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
50                 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
51    }
52
53    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
54        panic("register classification not implemented");
55        return false;
56    }
57
58    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
59        panic("register classification not implemented");
60        return false;
61    }
62
63    inline bool isCallerSaveFloatRegister(unsigned int reg) {
64        panic("register classification not implemented");
65        return false;
66    }
67
68    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
69        panic("register classification not implemented");
70        return false;
71    }
72
73    // Instruction address compression hooks
74    inline Addr realPCToFetchPC(const Addr &addr)
75    {
76        return addr;
77    }
78
79    inline Addr fetchPCToRealPC(const Addr &addr)
80    {
81        return addr;
82    }
83
84    // the size of "fetched" instructions (not necessarily the size
85    // of real instructions for PISA)
86    inline size_t fetchInstSize()
87    {
88        return sizeof(MachInst);
89    }
90
91    /**
92     * Function to insure ISA semantics about 0 registers.
93     * @param tc The thread context.
94     */
95    template <class TC>
96    void zeroRegisters(TC *tc);
97
98    inline void
99    initCPU(ThreadContext *tc, int cpuId)
100    {
101        static Fault por = new PowerOnReset();
102        if (cpuId == 0)
103            por->invoke(tc);
104
105    }
106
107    inline void
108    startupCPU(ThreadContext *tc, int cpuId)
109    {
110#if FULL_SYSTEM
111        // Other CPUs will get activated by IPIs
112        if (cpuId == 0)
113            tc->activate(0);
114#else
115        tc->activate(0);
116#endif
117    }
118
119    void copyRegs(ThreadContext *src, ThreadContext *dest);
120
121    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
122
123} // namespace SparcISA
124
125#endif
126