utility.hh revision 6335
111723Sar4jc@virginia.edu/*
211723Sar4jc@virginia.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan
311723Sar4jc@virginia.edu * All rights reserved.
411723Sar4jc@virginia.edu *
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611723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are
711723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright
811723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer;
911723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright
1011723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the
1111723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution;
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1411723Sar4jc@virginia.edu * this software without specific prior written permission.
1511723Sar4jc@virginia.edu *
1611723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1711723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1811723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1911723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2011723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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2511723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2611723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2711723Sar4jc@virginia.edu *
2811723Sar4jc@virginia.edu * Authors: Gabe Black
2911723Sar4jc@virginia.edu */
3011723Sar4jc@virginia.edu
3111723Sar4jc@virginia.edu#ifndef __ARCH_SPARC_UTILITY_HH__
3211723Sar4jc@virginia.edu#define __ARCH_SPARC_UTILITY_HH__
3311723Sar4jc@virginia.edu
3411723Sar4jc@virginia.edu#include "arch/sparc/faults.hh"
3511723Sar4jc@virginia.edu#include "arch/sparc/isa_traits.hh"
3611723Sar4jc@virginia.edu#include "arch/sparc/registers.hh"
3711723Sar4jc@virginia.edu#include "arch/sparc/tlb.hh"
3811723Sar4jc@virginia.edu#include "base/misc.hh"
3911723Sar4jc@virginia.edu#include "base/bitfield.hh"
4011723Sar4jc@virginia.edu#include "cpu/thread_context.hh"
4111723Sar4jc@virginia.edu
4211723Sar4jc@virginia.edunamespace SparcISA
4311723Sar4jc@virginia.edu{
4411723Sar4jc@virginia.edu
4511723Sar4jc@virginia.edu
4611723Sar4jc@virginia.edu    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
4711723Sar4jc@virginia.edu
4811723Sar4jc@virginia.edu    static inline bool
4911723Sar4jc@virginia.edu    inUserMode(ThreadContext *tc)
5011723Sar4jc@virginia.edu    {
5111723Sar4jc@virginia.edu        return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
5211723Sar4jc@virginia.edu                 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
5311723Sar4jc@virginia.edu    }
5411723Sar4jc@virginia.edu
5511723Sar4jc@virginia.edu    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
5611723Sar4jc@virginia.edu        panic("register classification not implemented");
5711723Sar4jc@virginia.edu        return false;
5811723Sar4jc@virginia.edu    }
5911723Sar4jc@virginia.edu
6011723Sar4jc@virginia.edu    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
6111723Sar4jc@virginia.edu        panic("register classification not implemented");
6211723Sar4jc@virginia.edu        return false;
6311961Sar4jc@virginia.edu    }
6411961Sar4jc@virginia.edu
6511723Sar4jc@virginia.edu    inline bool isCallerSaveFloatRegister(unsigned int reg) {
6611723Sar4jc@virginia.edu        panic("register classification not implemented");
6711723Sar4jc@virginia.edu        return false;
6811723Sar4jc@virginia.edu    }
6911723Sar4jc@virginia.edu
7011723Sar4jc@virginia.edu    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
7111723Sar4jc@virginia.edu        panic("register classification not implemented");
72        return false;
73    }
74
75    // Instruction address compression hooks
76    inline Addr realPCToFetchPC(const Addr &addr)
77    {
78        return addr;
79    }
80
81    inline Addr fetchPCToRealPC(const Addr &addr)
82    {
83        return addr;
84    }
85
86    // the size of "fetched" instructions (not necessarily the size
87    // of real instructions for PISA)
88    inline size_t fetchInstSize()
89    {
90        return sizeof(MachInst);
91    }
92
93    /**
94     * Function to insure ISA semantics about 0 registers.
95     * @param tc The thread context.
96     */
97    template <class TC>
98    void zeroRegisters(TC *tc);
99
100    inline void initCPU(ThreadContext *tc, int cpuId)
101    {
102        static Fault por = new PowerOnReset();
103        if (cpuId == 0)
104            por->invoke(tc);
105
106    }
107
108    inline void startupCPU(ThreadContext *tc, int cpuId)
109    {
110#if FULL_SYSTEM
111        // Other CPUs will get activated by IPIs
112        if (cpuId == 0)
113            tc->activate(0);
114#else
115        tc->activate(0);
116#endif
117    }
118
119    void copyRegs(ThreadContext *src, ThreadContext *dest);
120
121    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
122
123} // namespace SparcISA
124
125#endif
126