utility.hh revision 4240:cde9d7751cce
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_SPARC_UTILITY_HH__ 32#define __ARCH_SPARC_UTILITY_HH__ 33 34#include "arch/sparc/faults.hh" 35#include "arch/sparc/isa_traits.hh" 36#include "arch/sparc/tlb.hh" 37#include "base/misc.hh" 38#include "base/bitfield.hh" 39#include "cpu/thread_context.hh" 40 41namespace SparcISA 42{ 43 44 static inline bool 45 inUserMode(ThreadContext *tc) 46 { 47 return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) || 48 tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2))); 49 } 50 51 inline bool isCallerSaveIntegerRegister(unsigned int reg) { 52 panic("register classification not implemented"); 53 return false; 54 } 55 56 inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 57 panic("register classification not implemented"); 58 return false; 59 } 60 61 inline bool isCallerSaveFloatRegister(unsigned int reg) { 62 panic("register classification not implemented"); 63 return false; 64 } 65 66 inline bool isCalleeSaveFloatRegister(unsigned int reg) { 67 panic("register classification not implemented"); 68 return false; 69 } 70 71 // Instruction address compression hooks 72 inline Addr realPCToFetchPC(const Addr &addr) 73 { 74 return addr; 75 } 76 77 inline Addr fetchPCToRealPC(const Addr &addr) 78 { 79 return addr; 80 } 81 82 // the size of "fetched" instructions (not necessarily the size 83 // of real instructions for PISA) 84 inline size_t fetchInstSize() 85 { 86 return sizeof(MachInst); 87 } 88 89 /** 90 * Function to insure ISA semantics about 0 registers. 91 * @param tc The thread context. 92 */ 93 template <class TC> 94 void zeroRegisters(TC *tc); 95 96 inline void initCPU(ThreadContext *tc, int cpuId) 97 { 98 static Fault por = new PowerOnReset(); 99 if (cpuId == 0) 100 por->invoke(tc); 101 102 } 103 104 inline void startupCPU(ThreadContext *tc, int cpuId) 105 { 106#if FULL_SYSTEM 107 // Other CPUs will get activated by IPIs 108 if (cpuId == 0) 109 tc->activate(0); 110#else 111 tc->activate(0); 112#endif 113 } 114 115} // namespace SparcISA 116 117#endif 118