utility.cc revision 7678:f19b6a3a8cec
15647Sgblack@eecs.umich.edu/* 29544Sandreas.hansson@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * Redistribution and use in source and binary forms, with or without 68922Swilliam.wang@arm.com * modification, are permitted provided that the following conditions are 78922Swilliam.wang@arm.com * met: redistributions of source code must retain the above copyright 88922Swilliam.wang@arm.com * notice, this list of conditions and the following disclaimer; 98922Swilliam.wang@arm.com * redistributions in binary form must reproduce the above copyright 108922Swilliam.wang@arm.com * notice, this list of conditions and the following disclaimer in the 118922Swilliam.wang@arm.com * documentation and/or other materials provided with the distribution; 128922Swilliam.wang@arm.com * neither the name of the copyright holders nor the names of its 138922Swilliam.wang@arm.com * contributors may be used to endorse or promote products derived from 145647Sgblack@eecs.umich.edu * this software without specific prior written permission. 155647Sgblack@eecs.umich.edu * 165647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177087Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187087Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197087Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207087Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217087Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227087Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237087Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247087Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267087Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277087Snate@binkert.org * 287087Snate@binkert.org * Authors: Gabe Black 297087Snate@binkert.org * Ali Saidi 307087Snate@binkert.org */ 317087Snate@binkert.org 327087Snate@binkert.org#include "arch/sparc/faults.hh" 337087Snate@binkert.org#include "arch/sparc/utility.hh" 345647Sgblack@eecs.umich.edu#if FULL_SYSTEM 357087Snate@binkert.org#include "arch/sparc/vtophys.hh" 365647Sgblack@eecs.umich.edu#include "mem/vport.hh" 375647Sgblack@eecs.umich.edu#endif 385647Sgblack@eecs.umich.edu 395647Sgblack@eecs.umich.edunamespace SparcISA { 405647Sgblack@eecs.umich.edu 415647Sgblack@eecs.umich.edu 425647Sgblack@eecs.umich.edu//The caller uses %o0-%05 for the first 6 arguments even if their floating 435647Sgblack@eecs.umich.edu//point. Double precision floating point values take two registers/args. 445647Sgblack@eecs.umich.edu//Quads, structs, and unions are passed as pointers. All arguments beyond 455647Sgblack@eecs.umich.edu//the sixth are passed on the stack past the 16 word window save area, 465647Sgblack@eecs.umich.edu//space for the struct/union return pointer, and space reserved for the 475647Sgblack@eecs.umich.edu//first 6 arguments which the caller may use but doesn't have to. 485647Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int number, bool fp) { 495647Sgblack@eecs.umich.edu#if FULL_SYSTEM 505647Sgblack@eecs.umich.edu const int NumArgumentRegs = 6; 515647Sgblack@eecs.umich.edu if (number < NumArgumentRegs) { 528229Snate@binkert.org return tc->readIntReg(8 + number); 535647Sgblack@eecs.umich.edu } else { 545654Sgblack@eecs.umich.edu Addr sp = tc->readIntReg(StackPointerReg); 555647Sgblack@eecs.umich.edu VirtualPort *vp = tc->getVirtPort(); 568232Snate@binkert.org uint64_t arg = vp->read<uint64_t>(sp + 92 + 576137Sgblack@eecs.umich.edu (number-NumArgumentRegs) * sizeof(uint64_t)); 586137Sgblack@eecs.umich.edu return arg; 596137Sgblack@eecs.umich.edu } 605654Sgblack@eecs.umich.edu#else 616046Sgblack@eecs.umich.edu panic("getArgument() only implemented for FULL_SYSTEM\n"); 628781Sgblack@eecs.umich.edu M5_DUMMY_RETURN 635647Sgblack@eecs.umich.edu#endif 645648Sgblack@eecs.umich.edu} 655648Sgblack@eecs.umich.edu 665647Sgblack@eecs.umich.eduvoid 675647Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 685647Sgblack@eecs.umich.edu{ 695647Sgblack@eecs.umich.edu 705647Sgblack@eecs.umich.edu uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); 715647Sgblack@eecs.umich.edu 725647Sgblack@eecs.umich.edu // Read all the trap level dependent registers and save them off 735647Sgblack@eecs.umich.edu for(int i = 1; i <= MaxTL; i++) 745647Sgblack@eecs.umich.edu { 755648Sgblack@eecs.umich.edu src->setMiscRegNoEffect(MISCREG_TL, i); 765647Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TL, i); 775648Sgblack@eecs.umich.edu 785648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); 795648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); 805648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); 815648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); 825648Sgblack@eecs.umich.edu } 835648Sgblack@eecs.umich.edu 845648Sgblack@eecs.umich.edu // Save off the traplevel 855648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TL, tl); 865648Sgblack@eecs.umich.edu src->setMiscRegNoEffect(MISCREG_TL, tl); 875648Sgblack@eecs.umich.edu 885648Sgblack@eecs.umich.edu 895648Sgblack@eecs.umich.edu // ASRs 905648Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); 915648Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); 925648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); 935648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); 945648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); 955648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); 965648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); 975648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); 985648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); 995648Sgblack@eecs.umich.edu 1005648Sgblack@eecs.umich.edu // Priv Registers 1015648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); 1025648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); 1035648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); 1045648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); 1055648Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); 1065648Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); 1075648Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); 1085648Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); 1095648Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); 1105648Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); 1115648Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); 1125648Sgblack@eecs.umich.edu 1135648Sgblack@eecs.umich.edu // Hyperprivilged registers 1145648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); 1155648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); 1165648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); 1175648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 1185648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 1195648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, 1205648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); 1215648Sgblack@eecs.umich.edu 1225648Sgblack@eecs.umich.edu // FSR 1235648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); 1245648Sgblack@eecs.umich.edu 1255648Sgblack@eecs.umich.edu //Strand Status Register 1265648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 1275648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 1285648Sgblack@eecs.umich.edu 1295648Sgblack@eecs.umich.edu // MMU Registers 1305648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, 1315648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); 1325648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, 1335648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); 1345648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, 1355648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); 1365648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 1375648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); 1385648Sgblack@eecs.umich.edu 1395648Sgblack@eecs.umich.edu // Scratchpad Registers 1405648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, 1415648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); 1425648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, 1435648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); 1445648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, 1455648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); 1465648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, 1475648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); 1485648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, 1495648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); 1505648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, 1515648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); 1525648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, 1535648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); 1545648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, 1555648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); 1565648Sgblack@eecs.umich.edu 1575648Sgblack@eecs.umich.edu // Queue Registers 1585648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, 1595648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); 1605648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, 1615648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); 1625648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, 1635648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); 1645648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, 1655648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); 1665648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, 1675648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); 1685648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, 1695648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); 1705648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, 1715648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); 1725648Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, 1735648Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); 1745648Sgblack@eecs.umich.edu} 1755648Sgblack@eecs.umich.edu 1765648Sgblack@eecs.umich.eduvoid 1775648Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 1785648Sgblack@eecs.umich.edu{ 1795648Sgblack@eecs.umich.edu //First loop through the integer registers. 1805648Sgblack@eecs.umich.edu int old_gl = src->readMiscRegNoEffect(MISCREG_GL); 1815648Sgblack@eecs.umich.edu int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); 1825648Sgblack@eecs.umich.edu //Globals 1835648Sgblack@eecs.umich.edu for (int x = 0; x < MaxGL; ++x) { 1845648Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_GL, x); 1855648Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_GL, x); 1865648Sgblack@eecs.umich.edu // Skip %g0 which is always zero. 1875648Sgblack@eecs.umich.edu for (int y = 1; y < 8; y++) 1885648Sgblack@eecs.umich.edu dest->setIntReg(y, src->readIntReg(y)); 1895648Sgblack@eecs.umich.edu } 1905648Sgblack@eecs.umich.edu //Locals and ins. Outs are all also ins. 1915648Sgblack@eecs.umich.edu for (int x = 0; x < NWindows; ++x) { 1925648Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_CWP, x); 1935648Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_CWP, x); 1945648Sgblack@eecs.umich.edu for (int y = 16; y < 32; y++) 1955648Sgblack@eecs.umich.edu dest->setIntReg(y, src->readIntReg(y)); 1965648Sgblack@eecs.umich.edu } 1975648Sgblack@eecs.umich.edu //Microcode reg and pseudo int regs (misc regs in the integer regfile). 1985648Sgblack@eecs.umich.edu for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) 1995648Sgblack@eecs.umich.edu dest->setIntReg(y, src->readIntReg(y)); 2005648Sgblack@eecs.umich.edu 2015648Sgblack@eecs.umich.edu //Restore src's GL, CWP 2025648Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_GL, old_gl); 2035648Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_CWP, old_cwp); 2045648Sgblack@eecs.umich.edu 2055648Sgblack@eecs.umich.edu 2065648Sgblack@eecs.umich.edu // Then loop through the floating point registers. 2075648Sgblack@eecs.umich.edu for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { 2085648Sgblack@eecs.umich.edu dest->setFloatRegBits(i, src->readFloatRegBits(i)); 2095648Sgblack@eecs.umich.edu } 2105648Sgblack@eecs.umich.edu 2115648Sgblack@eecs.umich.edu // Copy misc. registers 2125648Sgblack@eecs.umich.edu copyMiscRegs(src, dest); 2135648Sgblack@eecs.umich.edu 2145648Sgblack@eecs.umich.edu 2155648Sgblack@eecs.umich.edu // Lastly copy PC/NPC 2165648Sgblack@eecs.umich.edu dest->setPC(src->readPC()); 2175648Sgblack@eecs.umich.edu dest->setNextPC(src->readNextPC()); 2185648Sgblack@eecs.umich.edu dest->setNextNPC(src->readNextNPC()); 2195648Sgblack@eecs.umich.edu} 2205649Sgblack@eecs.umich.edu 2215649Sgblack@eecs.umich.eduvoid 2225649Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId) 2235648Sgblack@eecs.umich.edu{ 2245898Sgblack@eecs.umich.edu static Fault por = new PowerOnReset(); 2255648Sgblack@eecs.umich.edu if (cpuId == 0) 2265648Sgblack@eecs.umich.edu por->invoke(tc); 2275648Sgblack@eecs.umich.edu} 2285648Sgblack@eecs.umich.edu 2295648Sgblack@eecs.umich.edu} //namespace SPARC_ISA 2305648Sgblack@eecs.umich.edu