utility.cc revision 6329
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#include "arch/sparc/utility.hh" 33#if FULL_SYSTEM 34#include "arch/sparc/vtophys.hh" 35#include "mem/vport.hh" 36#endif 37 38namespace SparcISA { 39 40 41//The caller uses %o0-%05 for the first 6 arguments even if their floating 42//point. Double precision floating point values take two registers/args. 43//Quads, structs, and unions are passed as pointers. All arguments beyond 44//the sixth are passed on the stack past the 16 word window save area, 45//space for the struct/union return pointer, and space reserved for the 46//first 6 arguments which the caller may use but doesn't have to. 47uint64_t getArgument(ThreadContext *tc, int number, bool fp) { 48#if FULL_SYSTEM 49 const int NumArgumentRegs = 6; 50 if (number < NumArgumentRegs) { 51 return tc->readIntReg(8 + number); 52 } else { 53 Addr sp = tc->readIntReg(StackPointerReg); 54 VirtualPort *vp = tc->getVirtPort(); 55 uint64_t arg = vp->read<uint64_t>(sp + 92 + 56 (number-NumArgumentRegs) * sizeof(uint64_t)); 57 return arg; 58 } 59#else 60 panic("getArgument() only implemented for FULL_SYSTEM\n"); 61 M5_DUMMY_RETURN 62#endif 63} 64 65void 66copyMiscRegs(ThreadContext *src, ThreadContext *dest) 67{ 68 69 uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); 70 71 // Read all the trap level dependent registers and save them off 72 for(int i = 1; i <= MaxTL; i++) 73 { 74 src->setMiscRegNoEffect(MISCREG_TL, i); 75 dest->setMiscRegNoEffect(MISCREG_TL, i); 76 77 dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); 78 dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); 79 dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); 80 dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); 81 } 82 83 // Save off the traplevel 84 dest->setMiscRegNoEffect(MISCREG_TL, tl); 85 src->setMiscRegNoEffect(MISCREG_TL, tl); 86 87 88 // ASRs 89// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); 90// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); 91 dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); 92 dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); 93 dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); 94 dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); 95 dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); 96 dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); 97 dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); 98 99 // Priv Registers 100 dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); 101 dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); 102 dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); 103 dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); 104 dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); 105// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); 106// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); 107// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); 108// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); 109// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); 110 dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); 111 112 // Hyperprivilged registers 113 dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); 114 dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); 115 dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); 116 dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 117 src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 118 dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, 119 src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); 120 121 // FSR 122 dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); 123 124 //Strand Status Register 125 dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 126 src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 127 128 // MMU Registers 129 dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, 130 src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); 131 dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, 132 src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); 133 dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, 134 src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); 135 dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 136 src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); 137 138 // Scratchpad Registers 139 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, 140 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); 141 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, 142 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); 143 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, 144 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); 145 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, 146 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); 147 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, 148 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); 149 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, 150 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); 151 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, 152 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); 153 dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, 154 src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); 155 156 // Queue Registers 157 dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, 158 src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); 159 dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, 160 src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); 161 dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, 162 src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); 163 dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, 164 src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); 165 dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, 166 src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); 167 dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, 168 src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); 169 dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, 170 src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); 171 dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, 172 src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); 173} 174 175void 176copyRegs(ThreadContext *src, ThreadContext *dest) 177{ 178 //First loop through the integer registers. 179 int old_gl = src->readMiscRegNoEffect(MISCREG_GL); 180 int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); 181 //Globals 182 for (int x = 0; x < MaxGL; ++x) { 183 src->setMiscRegNoEffect(MISCREG_GL, x); 184 dest->setMiscRegNoEffect(MISCREG_GL, x); 185 // Skip %g0 which is always zero. 186 for (int y = 1; y < 8; y++) 187 dest->setIntReg(y, src->readIntReg(y)); 188 } 189 //Locals and ins. Outs are all also ins. 190 for (int x = 0; x < NWindows; ++x) { 191 src->setMiscRegNoEffect(MISCREG_CWP, x); 192 dest->setMiscRegNoEffect(MISCREG_CWP, x); 193 for (int y = 16; y < 32; y++) 194 dest->setIntReg(y, src->readIntReg(y)); 195 } 196 //Microcode reg and pseudo int regs (misc regs in the integer regfile). 197 for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) 198 dest->setIntReg(y, src->readIntReg(y)); 199 200 //Restore src's GL, CWP 201 src->setMiscRegNoEffect(MISCREG_GL, old_gl); 202 src->setMiscRegNoEffect(MISCREG_CWP, old_cwp); 203 204 205 // Then loop through the floating point registers. 206 for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { 207 dest->setFloatRegBits(i, src->readFloatRegBits(i)); 208 } 209 210 // Copy misc. registers 211 copyMiscRegs(src, dest); 212 213 214 // Lastly copy PC/NPC 215 dest->setPC(src->readPC()); 216 dest->setNextPC(src->readNextPC()); 217 dest->setNextNPC(src->readNextNPC()); 218} 219} //namespace SPARC_ISA 220