utility.cc revision 13915
15222Sksewell@umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * All rights reserved. 45254Sksewell@umich.edu * 55222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 155254Sksewell@umich.edu * 165222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275254Sksewell@umich.edu * 285222Sksewell@umich.edu * Authors: Gabe Black 295254Sksewell@umich.edu * Ali Saidi 305254Sksewell@umich.edu */ 315254Sksewell@umich.edu 325222Sksewell@umich.edu#include "arch/sparc/utility.hh" 335222Sksewell@umich.edu 345222Sksewell@umich.edu#include "arch/sparc/faults.hh" 355222Sksewell@umich.edu#include "arch/sparc/vtophys.hh" 365222Sksewell@umich.edu#include "mem/fs_translating_port_proxy.hh" 375222Sksewell@umich.edu 385222Sksewell@umich.edunamespace SparcISA { 395222Sksewell@umich.edu 405222Sksewell@umich.edu 415222Sksewell@umich.edu// The caller uses %o0-%05 for the first 6 arguments even if their floating 425222Sksewell@umich.edu// point. Double precision floating point values take two registers/args. 435222Sksewell@umich.edu// Quads, structs, and unions are passed as pointers. All arguments beyond 445222Sksewell@umich.edu// the sixth are passed on the stack past the 16 word window save area, 455222Sksewell@umich.edu// space for the struct/union return pointer, and space reserved for the 465222Sksewell@umich.edu// first 6 arguments which the caller may use but doesn't have to. 475222Sksewell@umich.eduuint64_t 485222Sksewell@umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 495222Sksewell@umich.edu{ 505222Sksewell@umich.edu if (!FullSystem) { 515222Sksewell@umich.edu panic("getArgument() only implemented for full system\n"); 525222Sksewell@umich.edu M5_DUMMY_RETURN 535222Sksewell@umich.edu } 545222Sksewell@umich.edu 555222Sksewell@umich.edu const int NumArgumentRegs = 6; 565222Sksewell@umich.edu if (number < NumArgumentRegs) { 575222Sksewell@umich.edu return tc->readIntReg(8 + number); 585222Sksewell@umich.edu } else { 595222Sksewell@umich.edu Addr sp = tc->readIntReg(StackPointerReg); 605222Sksewell@umich.edu FSTranslatingPortProxy &vp = tc->getVirtProxy(); 615222Sksewell@umich.edu uint64_t arg = vp.read<uint64_t>(sp + 92 + 625222Sksewell@umich.edu (number-NumArgumentRegs) * sizeof(uint64_t)); 635222Sksewell@umich.edu return arg; 645222Sksewell@umich.edu } 655222Sksewell@umich.edu} 665222Sksewell@umich.edu 675222Sksewell@umich.eduvoid 685222Sksewell@umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 695222Sksewell@umich.edu{ 705222Sksewell@umich.edu 715222Sksewell@umich.edu uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); 725222Sksewell@umich.edu 735222Sksewell@umich.edu // Read all the trap level dependent registers and save them off 745222Sksewell@umich.edu for (int i = 1; i <= MaxTL; i++) { 755222Sksewell@umich.edu src->setMiscRegNoEffect(MISCREG_TL, i); 765222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TL, i); 775222Sksewell@umich.edu 785222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TT, 795704Snate@binkert.org src->readMiscRegNoEffect(MISCREG_TT)); 805222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TPC, 815222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_TPC)); 825222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TNPC, 835222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_TNPC)); 845222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TSTATE, 855222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_TSTATE)); 865222Sksewell@umich.edu } 875222Sksewell@umich.edu 885222Sksewell@umich.edu // Save off the traplevel 895222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TL, tl); 905222Sksewell@umich.edu src->setMiscRegNoEffect(MISCREG_TL, tl); 915222Sksewell@umich.edu 925222Sksewell@umich.edu 935222Sksewell@umich.edu // ASRs 945222Sksewell@umich.edu// dest->setMiscRegNoEffect(MISCREG_Y, 955222Sksewell@umich.edu// src->readMiscRegNoEffect(MISCREG_Y)); 965222Sksewell@umich.edu// dest->setMiscRegNoEffect(MISCREG_CCR, 975222Sksewell@umich.edu// src->readMiscRegNoEffect(MISCREG_CCR)); 985222Sksewell@umich.edu dest->setMiscReg(MISCREG_ASI, 995222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_ASI)); 1005222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TICK, 1015222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_TICK)); 1025222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_FPRS, 1035222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_FPRS)); 1045222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_SOFTINT, 1055222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_SOFTINT)); 1065222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, 1075222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); 1085222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_STICK, 1095222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_STICK)); 1105222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, 1115222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); 1125222Sksewell@umich.edu 1135222Sksewell@umich.edu // Priv Registers 1145222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TICK, 1155222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_TICK)); 1165222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_TBA, 1175222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_TBA)); 1185222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_PSTATE, 1195222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_PSTATE)); 1205222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_PIL, 1215222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_PIL)); 1225222Sksewell@umich.edu dest->setMiscReg(MISCREG_CWP, 1235222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_CWP)); 1245222Sksewell@umich.edu// dest->setMiscRegNoEffect(MISCREG_CANSAVE, 1255222Sksewell@umich.edu// src->readMiscRegNoEffect(MISCREG_CANSAVE)); 1265222Sksewell@umich.edu// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, 1275222Sksewell@umich.edu// src->readMiscRegNoEffect(MISCREG_CANRESTORE)); 1285222Sksewell@umich.edu// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, 1295222Sksewell@umich.edu// src->readMiscRegNoEffect(MISCREG_OTHERWIN)); 1305222Sksewell@umich.edu// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, 1315222Sksewell@umich.edu// src->readMiscRegNoEffect(MISCREG_CLEANWIN)); 1325222Sksewell@umich.edu// dest->setMiscRegNoEffect(MISCREG_WSTATE, 1335222Sksewell@umich.edu// src->readMiscRegNoEffect(MISCREG_WSTATE)); 1345222Sksewell@umich.edu dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); 1355222Sksewell@umich.edu 1365222Sksewell@umich.edu // Hyperprivilged registers 1375222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_HPSTATE, 1385222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_HPSTATE)); 1395222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_HINTP, 1405222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_HINTP)); 1415222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_HTBA, 1425222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_HTBA)); 1435222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 1445222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 1455222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, 1465222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); 1475222Sksewell@umich.edu 1485222Sksewell@umich.edu // FSR 1495222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_FSR, 1505222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_FSR)); 1515222Sksewell@umich.edu 1525222Sksewell@umich.edu // Strand Status Register 1535222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 1545222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 1555222Sksewell@umich.edu 1565222Sksewell@umich.edu // MMU Registers 1575222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, 1585222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); 1595222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, 1605222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); 1615222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, 1625222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); 1635222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 1645222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); 1655222Sksewell@umich.edu 1665222Sksewell@umich.edu // Scratchpad Registers 1675222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, 1685222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); 1695222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, 1705222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); 1715222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, 1725222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); 1735222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, 1745222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); 1755222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, 1765222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); 1775222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, 1785222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); 1795222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, 1805222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); 1815222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, 1825222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); 1835222Sksewell@umich.edu 1845222Sksewell@umich.edu // Queue Registers 1855222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, 1865222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); 1875222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, 1885222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); 1895222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, 1905222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); 1915222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, 1925704Snate@binkert.org src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); 1935222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, 1945222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); 1955222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, 1965222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); 1975222Sksewell@umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, 1985222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); 1995704Snate@binkert.org dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, 2005222Sksewell@umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); 2015222Sksewell@umich.edu} 2025222Sksewell@umich.edu 2035222Sksewell@umich.eduvoid 2045222Sksewell@umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 2055222Sksewell@umich.edu{ 2065222Sksewell@umich.edu // First loop through the integer registers. 2075222Sksewell@umich.edu int old_gl = src->readMiscRegNoEffect(MISCREG_GL); 2085222Sksewell@umich.edu int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); 2095222Sksewell@umich.edu // Globals 2105222Sksewell@umich.edu for (int x = 0; x < MaxGL; ++x) { 2115222Sksewell@umich.edu src->setMiscReg(MISCREG_GL, x); 2125222Sksewell@umich.edu dest->setMiscReg(MISCREG_GL, x); 2135222Sksewell@umich.edu // Skip %g0 which is always zero. 2145222Sksewell@umich.edu for (int y = 1; y < 8; y++) 2155222Sksewell@umich.edu dest->setIntReg(y, src->readIntReg(y)); 2165222Sksewell@umich.edu } 2175222Sksewell@umich.edu // Locals and ins. Outs are all also ins. 2185222Sksewell@umich.edu for (int x = 0; x < NWindows; ++x) { 2195222Sksewell@umich.edu src->setMiscReg(MISCREG_CWP, x); 2205222Sksewell@umich.edu dest->setMiscReg(MISCREG_CWP, x); 2215222Sksewell@umich.edu for (int y = 16; y < 32; y++) 2225222Sksewell@umich.edu dest->setIntReg(y, src->readIntReg(y)); 2235222Sksewell@umich.edu } 2245222Sksewell@umich.edu // Microcode reg and pseudo int regs (misc regs in the integer regfile). 2255222Sksewell@umich.edu for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) 2265222Sksewell@umich.edu dest->setIntReg(y, src->readIntReg(y)); 2275222Sksewell@umich.edu 2285222Sksewell@umich.edu // Restore src's GL, CWP 2295222Sksewell@umich.edu src->setMiscReg(MISCREG_GL, old_gl); 2305222Sksewell@umich.edu src->setMiscReg(MISCREG_CWP, old_cwp); 2315222Sksewell@umich.edu 2325222Sksewell@umich.edu 2335222Sksewell@umich.edu // Then loop through the floating point registers. 2345222Sksewell@umich.edu for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { 2355222Sksewell@umich.edu dest->setFloatReg(i, src->readFloatReg(i)); 2365222Sksewell@umich.edu } 2375222Sksewell@umich.edu 2385222Sksewell@umich.edu // Would need to add condition-code regs if implemented 2395222Sksewell@umich.edu assert(NumCCRegs == 0); 2405222Sksewell@umich.edu 2415222Sksewell@umich.edu // Copy misc. registers 2425222Sksewell@umich.edu copyMiscRegs(src, dest); 2435222Sksewell@umich.edu 2445222Sksewell@umich.edu // Lastly copy PC/NPC 2455222Sksewell@umich.edu dest->pcState(src->pcState()); 2465222Sksewell@umich.edu} 2475222Sksewell@umich.edu 2485222Sksewell@umich.eduvoid 2495222Sksewell@umich.eduskipFunction(ThreadContext *tc) 2505222Sksewell@umich.edu{ 2515222Sksewell@umich.edu PCState newPC = tc->pcState(); 2525222Sksewell@umich.edu newPC.set(tc->readIntReg(ReturnAddressReg)); 2535222Sksewell@umich.edu tc->pcState(newPC); 2545222Sksewell@umich.edu} 2555222Sksewell@umich.edu 2565222Sksewell@umich.edu 2575222Sksewell@umich.eduvoid 2585222Sksewell@umich.eduinitCPU(ThreadContext *tc, int cpuId) 2595222Sksewell@umich.edu{ 2605222Sksewell@umich.edu static Fault por = std::make_shared<PowerOnReset>(); 2615222Sksewell@umich.edu if (cpuId == 0) 2625222Sksewell@umich.edu por->invoke(tc); 2635222Sksewell@umich.edu} 2645222Sksewell@umich.edu 2655222Sksewell@umich.edu} // namespace SPARC_ISA 2665222Sksewell@umich.edu