utility.cc revision 7720
14826Ssaidi@eecs.umich.edu/* 24826Ssaidi@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 34826Ssaidi@eecs.umich.edu * All rights reserved. 44826Ssaidi@eecs.umich.edu * 54826Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64826Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 74826Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84826Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94826Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104826Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114826Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124826Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134826Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144826Ssaidi@eecs.umich.edu * this software without specific prior written permission. 154826Ssaidi@eecs.umich.edu * 164826Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174826Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184826Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194826Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204826Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214826Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224826Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234826Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244826Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254826Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264826Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274826Ssaidi@eecs.umich.edu * 284826Ssaidi@eecs.umich.edu * Authors: Gabe Black 294826Ssaidi@eecs.umich.edu * Ali Saidi 304826Ssaidi@eecs.umich.edu */ 314826Ssaidi@eecs.umich.edu 327678Sgblack@eecs.umich.edu#include "arch/sparc/faults.hh" 334826Ssaidi@eecs.umich.edu#include "arch/sparc/utility.hh" 344826Ssaidi@eecs.umich.edu#if FULL_SYSTEM 354826Ssaidi@eecs.umich.edu#include "arch/sparc/vtophys.hh" 364826Ssaidi@eecs.umich.edu#include "mem/vport.hh" 374826Ssaidi@eecs.umich.edu#endif 384826Ssaidi@eecs.umich.edu 394826Ssaidi@eecs.umich.edunamespace SparcISA { 404826Ssaidi@eecs.umich.edu 414826Ssaidi@eecs.umich.edu 424826Ssaidi@eecs.umich.edu//The caller uses %o0-%05 for the first 6 arguments even if their floating 434826Ssaidi@eecs.umich.edu//point. Double precision floating point values take two registers/args. 444826Ssaidi@eecs.umich.edu//Quads, structs, and unions are passed as pointers. All arguments beyond 454826Ssaidi@eecs.umich.edu//the sixth are passed on the stack past the 16 word window save area, 464826Ssaidi@eecs.umich.edu//space for the struct/union return pointer, and space reserved for the 474826Ssaidi@eecs.umich.edu//first 6 arguments which the caller may use but doesn't have to. 487707Sgblack@eecs.umich.eduuint64_t 497707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 507707Sgblack@eecs.umich.edu{ 514826Ssaidi@eecs.umich.edu#if FULL_SYSTEM 525958Sgblack@eecs.umich.edu const int NumArgumentRegs = 6; 534826Ssaidi@eecs.umich.edu if (number < NumArgumentRegs) { 545958Sgblack@eecs.umich.edu return tc->readIntReg(8 + number); 554826Ssaidi@eecs.umich.edu } else { 564826Ssaidi@eecs.umich.edu Addr sp = tc->readIntReg(StackPointerReg); 575498Ssaidi@eecs.umich.edu VirtualPort *vp = tc->getVirtPort(); 584826Ssaidi@eecs.umich.edu uint64_t arg = vp->read<uint64_t>(sp + 92 + 594826Ssaidi@eecs.umich.edu (number-NumArgumentRegs) * sizeof(uint64_t)); 604826Ssaidi@eecs.umich.edu return arg; 614826Ssaidi@eecs.umich.edu } 624826Ssaidi@eecs.umich.edu#else 634826Ssaidi@eecs.umich.edu panic("getArgument() only implemented for FULL_SYSTEM\n"); 644826Ssaidi@eecs.umich.edu M5_DUMMY_RETURN 654826Ssaidi@eecs.umich.edu#endif 664826Ssaidi@eecs.umich.edu} 676329Sgblack@eecs.umich.edu 686329Sgblack@eecs.umich.eduvoid 696329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 706329Sgblack@eecs.umich.edu{ 716329Sgblack@eecs.umich.edu 726329Sgblack@eecs.umich.edu uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL); 736329Sgblack@eecs.umich.edu 746329Sgblack@eecs.umich.edu // Read all the trap level dependent registers and save them off 756329Sgblack@eecs.umich.edu for(int i = 1; i <= MaxTL; i++) 766329Sgblack@eecs.umich.edu { 776329Sgblack@eecs.umich.edu src->setMiscRegNoEffect(MISCREG_TL, i); 786329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TL, i); 796329Sgblack@eecs.umich.edu 806329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT)); 816329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC)); 826329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC)); 836329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE)); 846329Sgblack@eecs.umich.edu } 856329Sgblack@eecs.umich.edu 866329Sgblack@eecs.umich.edu // Save off the traplevel 876329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TL, tl); 886329Sgblack@eecs.umich.edu src->setMiscRegNoEffect(MISCREG_TL, tl); 896329Sgblack@eecs.umich.edu 906329Sgblack@eecs.umich.edu 916329Sgblack@eecs.umich.edu // ASRs 926329Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y)); 936329Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR)); 946329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI)); 956329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); 966329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS)); 976329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT)); 986329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR)); 996329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK)); 1006329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR)); 1016329Sgblack@eecs.umich.edu 1026329Sgblack@eecs.umich.edu // Priv Registers 1036329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK)); 1046329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA)); 1056329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE)); 1066329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL)); 1076337Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP)); 1086329Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE)); 1096329Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE)); 1106329Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN)); 1116329Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN)); 1126329Sgblack@eecs.umich.edu// dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE)); 1136337Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL)); 1146329Sgblack@eecs.umich.edu 1156329Sgblack@eecs.umich.edu // Hyperprivilged registers 1166329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE)); 1176329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP)); 1186329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA)); 1196329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 1206329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 1216329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR, 1226329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR)); 1236329Sgblack@eecs.umich.edu 1246329Sgblack@eecs.umich.edu // FSR 1256329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR)); 1266329Sgblack@eecs.umich.edu 1276329Sgblack@eecs.umich.edu //Strand Status Register 1286329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG, 1296329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG)); 1306329Sgblack@eecs.umich.edu 1316329Sgblack@eecs.umich.edu // MMU Registers 1326329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT, 1336329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT)); 1346329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT, 1356329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT)); 1366329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID, 1376329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_PART_ID)); 1386329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 1396329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL)); 1406329Sgblack@eecs.umich.edu 1416329Sgblack@eecs.umich.edu // Scratchpad Registers 1426329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0, 1436329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0)); 1446329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1, 1456329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1)); 1466329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2, 1476329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2)); 1486329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3, 1496329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3)); 1506329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4, 1516329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4)); 1526329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5, 1536329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5)); 1546329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6, 1556329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6)); 1566329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7, 1576329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7)); 1586329Sgblack@eecs.umich.edu 1596329Sgblack@eecs.umich.edu // Queue Registers 1606329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD, 1616329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD)); 1626329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL, 1636329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL)); 1646329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD, 1656329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD)); 1666329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL, 1676329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL)); 1686329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD, 1696329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD)); 1706329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL, 1716329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL)); 1726329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD, 1736329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD)); 1746329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL, 1756329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL)); 1766329Sgblack@eecs.umich.edu} 1776329Sgblack@eecs.umich.edu 1786329Sgblack@eecs.umich.eduvoid 1796329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 1806329Sgblack@eecs.umich.edu{ 1816329Sgblack@eecs.umich.edu //First loop through the integer registers. 1826329Sgblack@eecs.umich.edu int old_gl = src->readMiscRegNoEffect(MISCREG_GL); 1836329Sgblack@eecs.umich.edu int old_cwp = src->readMiscRegNoEffect(MISCREG_CWP); 1846329Sgblack@eecs.umich.edu //Globals 1856329Sgblack@eecs.umich.edu for (int x = 0; x < MaxGL; ++x) { 1866337Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_GL, x); 1876337Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_GL, x); 1886329Sgblack@eecs.umich.edu // Skip %g0 which is always zero. 1896329Sgblack@eecs.umich.edu for (int y = 1; y < 8; y++) 1906329Sgblack@eecs.umich.edu dest->setIntReg(y, src->readIntReg(y)); 1916329Sgblack@eecs.umich.edu } 1926329Sgblack@eecs.umich.edu //Locals and ins. Outs are all also ins. 1936329Sgblack@eecs.umich.edu for (int x = 0; x < NWindows; ++x) { 1946337Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_CWP, x); 1956337Sgblack@eecs.umich.edu dest->setMiscReg(MISCREG_CWP, x); 1966329Sgblack@eecs.umich.edu for (int y = 16; y < 32; y++) 1976329Sgblack@eecs.umich.edu dest->setIntReg(y, src->readIntReg(y)); 1986329Sgblack@eecs.umich.edu } 1996329Sgblack@eecs.umich.edu //Microcode reg and pseudo int regs (misc regs in the integer regfile). 2006329Sgblack@eecs.umich.edu for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y) 2016329Sgblack@eecs.umich.edu dest->setIntReg(y, src->readIntReg(y)); 2026329Sgblack@eecs.umich.edu 2036329Sgblack@eecs.umich.edu //Restore src's GL, CWP 2046337Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_GL, old_gl); 2056337Sgblack@eecs.umich.edu src->setMiscReg(MISCREG_CWP, old_cwp); 2066329Sgblack@eecs.umich.edu 2076329Sgblack@eecs.umich.edu 2086329Sgblack@eecs.umich.edu // Then loop through the floating point registers. 2096329Sgblack@eecs.umich.edu for (int i = 0; i < SparcISA::NumFloatArchRegs; ++i) { 2106329Sgblack@eecs.umich.edu dest->setFloatRegBits(i, src->readFloatRegBits(i)); 2116329Sgblack@eecs.umich.edu } 2126329Sgblack@eecs.umich.edu 2136329Sgblack@eecs.umich.edu // Copy misc. registers 2146329Sgblack@eecs.umich.edu copyMiscRegs(src, dest); 2156329Sgblack@eecs.umich.edu 2166329Sgblack@eecs.umich.edu // Lastly copy PC/NPC 2177720Sgblack@eecs.umich.edu dest->pcState(src->pcState()); 2186329Sgblack@eecs.umich.edu} 2197678Sgblack@eecs.umich.edu 2207678Sgblack@eecs.umich.eduvoid 2217693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 2227693SAli.Saidi@ARM.com{ 2237720Sgblack@eecs.umich.edu TheISA::PCState newPC = tc->pcState(); 2247720Sgblack@eecs.umich.edu newPC.set(tc->readIntReg(ReturnAddressReg)); 2257720Sgblack@eecs.umich.edu tc->pcState(newPC); 2267693SAli.Saidi@ARM.com} 2277693SAli.Saidi@ARM.com 2287693SAli.Saidi@ARM.com 2297693SAli.Saidi@ARM.comvoid 2307678Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId) 2317678Sgblack@eecs.umich.edu{ 2327678Sgblack@eecs.umich.edu static Fault por = new PowerOnReset(); 2337678Sgblack@eecs.umich.edu if (cpuId == 0) 2347678Sgblack@eecs.umich.edu por->invoke(tc); 2357678Sgblack@eecs.umich.edu} 2367678Sgblack@eecs.umich.edu 2374826Ssaidi@eecs.umich.edu} //namespace SPARC_ISA 238