ua2005.cc revision 4185:42c0395a03f9 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/miscregfile.hh"
30#include "base/bitfield.hh"
31#include "base/trace.hh"
32#include "cpu/base.hh"
33#include "cpu/thread_context.hh"
34
35using namespace SparcISA;
36
37
38void
39MiscRegFile::checkSoftInt(ThreadContext *tc)
40{
41    // If PIL < 14, copy over the tm and sm bits
42    if (pil < 14 && softint & 0x10000)
43        tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,16);
44    else
45        tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,16);
46    if (pil < 14 && softint & 0x1)
47        tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,0);
48    else
49        tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,0);
50
51    // Copy over any of the other bits that are set
52    for (int bit = 15; bit > 0; --bit) {
53        if (1 << bit & softint && bit > pil)
54            tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,bit);
55        else
56            tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,bit);
57    }
58}
59
60
61void
62MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
63{
64    int64_t time;
65    switch (miscReg) {
66        /* Full system only ASRs */
67      case MISCREG_SOFTINT:
68        setRegNoEffect(miscReg, val);;
69        checkSoftInt(tc);
70        break;
71      case MISCREG_SOFTINT_CLR:
72        return setReg(MISCREG_SOFTINT, ~val & softint, tc);
73      case MISCREG_SOFTINT_SET:
74        return setReg(MISCREG_SOFTINT, val | softint, tc);
75
76      case MISCREG_TICK_CMPR:
77        if (tickCompare == NULL)
78            tickCompare = new TickCompareEvent(this, tc);
79        setRegNoEffect(miscReg, val);
80        if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
81            tickCompare->deschedule();
82        time = (tick_cmpr & mask(63)) - (tick & mask(63));
83        if (!(tick_cmpr & ~mask(63)) && time > 0) {
84            if (tickCompare->scheduled())
85                tickCompare->deschedule();
86            tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
87        }
88        panic("writing to TICK compare register %#X\n", val);
89        break;
90
91      case MISCREG_STICK_CMPR:
92        if (sTickCompare == NULL)
93            sTickCompare = new STickCompareEvent(this, tc);
94        setRegNoEffect(miscReg, val);
95        if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
96            sTickCompare->deschedule();
97        time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
98            tc->getCpuPtr()->instCount();
99        if (!(stick_cmpr & ~mask(63)) && time > 0) {
100            if (sTickCompare->scheduled())
101                sTickCompare->deschedule();
102            sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
103        }
104        DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
105        break;
106
107      case MISCREG_PSTATE:
108        setRegNoEffect(miscReg, val);
109
110      case MISCREG_PIL:
111        setRegNoEffect(miscReg, val);
112        checkSoftInt(tc);
113        break;
114
115      case MISCREG_HVER:
116        panic("Shouldn't be writing HVER\n");
117
118      case MISCREG_HINTP:
119        setRegNoEffect(miscReg, val);
120        if (hintp)
121            tc->getCpuPtr()->post_interrupt(IT_HINTP,0);
122        else
123            tc->getCpuPtr()->clear_interrupt(IT_HINTP,0);
124        break;
125
126      case MISCREG_HTBA:
127        // clear lower 7 bits on writes.
128        setRegNoEffect(miscReg, val & ULL(~0x7FFF));
129        break;
130
131      case MISCREG_QUEUE_CPU_MONDO_HEAD:
132      case MISCREG_QUEUE_CPU_MONDO_TAIL:
133        setRegNoEffect(miscReg, val);
134        if (cpu_mondo_head != cpu_mondo_tail)
135            tc->getCpuPtr()->post_interrupt(IT_CPU_MONDO,0);
136        else
137            tc->getCpuPtr()->clear_interrupt(IT_CPU_MONDO,0);
138        break;
139      case MISCREG_QUEUE_DEV_MONDO_HEAD:
140      case MISCREG_QUEUE_DEV_MONDO_TAIL:
141        setRegNoEffect(miscReg, val);
142        if (dev_mondo_head != dev_mondo_tail)
143            tc->getCpuPtr()->post_interrupt(IT_DEV_MONDO,0);
144        else
145            tc->getCpuPtr()->clear_interrupt(IT_DEV_MONDO,0);
146        break;
147      case MISCREG_QUEUE_RES_ERROR_HEAD:
148      case MISCREG_QUEUE_RES_ERROR_TAIL:
149        setRegNoEffect(miscReg, val);
150        if (res_error_head != res_error_tail)
151            tc->getCpuPtr()->post_interrupt(IT_RES_ERROR,0);
152        else
153            tc->getCpuPtr()->clear_interrupt(IT_RES_ERROR,0);
154        break;
155      case MISCREG_QUEUE_NRES_ERROR_HEAD:
156      case MISCREG_QUEUE_NRES_ERROR_TAIL:
157        setRegNoEffect(miscReg, val);
158        // This one doesn't have an interrupt to report to the guest OS
159        break;
160
161      case MISCREG_HSTICK_CMPR:
162        if (hSTickCompare == NULL)
163            hSTickCompare = new HSTickCompareEvent(this, tc);
164        setRegNoEffect(miscReg, val);
165        if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
166            hSTickCompare->deschedule();
167        time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
168            tc->getCpuPtr()->instCount();
169        if (!(hstick_cmpr & ~mask(63)) && time > 0) {
170            if (hSTickCompare->scheduled())
171                hSTickCompare->deschedule();
172            hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
173        }
174        DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
175        break;
176
177      case MISCREG_HPSTATE:
178        // T1000 spec says impl. dependent val must always be 1
179        setRegNoEffect(miscReg, val | HPSTATE::id);
180#if FULL_SYSTEM
181        if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
182            tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
183        else
184            tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
185#endif
186        break;
187      case MISCREG_HTSTATE:
188      case MISCREG_STRAND_STS_REG:
189        setRegNoEffect(miscReg, val);
190        break;
191
192      default:
193        panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
194    }
195}
196
197MiscReg
198MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
199{
200    switch (miscReg) {
201        /* Privileged registers. */
202      case MISCREG_QUEUE_CPU_MONDO_HEAD:
203      case MISCREG_QUEUE_CPU_MONDO_TAIL:
204      case MISCREG_QUEUE_DEV_MONDO_HEAD:
205      case MISCREG_QUEUE_DEV_MONDO_TAIL:
206      case MISCREG_QUEUE_RES_ERROR_HEAD:
207      case MISCREG_QUEUE_RES_ERROR_TAIL:
208      case MISCREG_QUEUE_NRES_ERROR_HEAD:
209      case MISCREG_QUEUE_NRES_ERROR_TAIL:
210      case MISCREG_SOFTINT:
211      case MISCREG_TICK_CMPR:
212      case MISCREG_STICK_CMPR:
213      case MISCREG_PIL:
214      case MISCREG_HPSTATE:
215      case MISCREG_HINTP:
216      case MISCREG_HTSTATE:
217      case MISCREG_STRAND_STS_REG:
218      case MISCREG_HSTICK_CMPR:
219        return readRegNoEffect(miscReg) ;
220
221      case MISCREG_HTBA:
222        return readRegNoEffect(miscReg) & ULL(~0x7FFF);
223      case MISCREG_HVER:
224        return NWindows | MaxTL << 8 | MaxGL << 16;
225
226      default:
227        panic("Invalid read to FS misc register\n");
228    }
229}
230/*
231  In Niagra STICK==TICK so this isn't needed
232  case MISCREG_STICK:
233  SparcSystem *sys;
234  sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
235  assert(sys != NULL);
236  return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
237*/
238
239
240
241void
242MiscRegFile::processTickCompare(ThreadContext *tc)
243{
244    panic("tick compare not implemented\n");
245}
246
247void
248MiscRegFile::processSTickCompare(ThreadContext *tc)
249{
250    // since our microcode instructions take two cycles we need to check if
251    // we're actually at the correct cycle or we need to wait a little while
252    // more
253    int ticks;
254    ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
255        tc->getCpuPtr()->instCount();
256    assert(ticks >= 0 && "stick compare missed interrupt cycle");
257
258    if (ticks == 0) {
259        DPRINTF(Timer, "STick compare cycle reached at %#x\n",
260                (stick_cmpr & mask(63)));
261        if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
262            setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
263        }
264    } else
265        sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
266}
267
268void
269MiscRegFile::processHSTickCompare(ThreadContext *tc)
270{
271    // since our microcode instructions take two cycles we need to check if
272    // we're actually at the correct cycle or we need to wait a little while
273    // more
274    int ticks;
275    ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
276        tc->getCpuPtr()->instCount();
277    assert(ticks >= 0 && "hstick compare missed interrupt cycle");
278
279    if (ticks == 0) {
280        DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
281                (stick_cmpr & mask(63)));
282        if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
283            setReg(MISCREG_HINTP, 1, tc);
284        }
285        // Need to do something to cause interrupt to happen here !!! @todo
286    } else
287        hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
288}
289
290