ua2005.cc revision 3899:389e4ea5f98e 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/miscregfile.hh"
32#include "base/bitfield.hh"
33#include "base/trace.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36
37using namespace SparcISA;
38
39void
40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
41        ThreadContext *tc)
42{
43    int64_t time;
44    switch (miscReg) {
45        /* Full system only ASRs */
46        case MISCREG_SOFTINT:
47          // Check if we are going to interrupt because of something
48          setReg(miscReg, val);
49          tc->getCpuPtr()->checkInterrupts = true;
50          if (val != 0x10000 && val != 0)
51              warn("Writing to softint not really supported, writing: %#x\n", val);
52          break;
53
54        case MISCREG_SOFTINT_CLR:
55          return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
56        case MISCREG_SOFTINT_SET:
57          return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
58
59        case MISCREG_TICK_CMPR:
60          if (tickCompare == NULL)
61              tickCompare = new TickCompareEvent(this, tc);
62          setReg(miscReg, val);
63          if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
64                  tickCompare->deschedule();
65          time = (tick_cmpr & mask(63)) - (tick & mask(63));
66          if (!(tick_cmpr & ~mask(63)) && time > 0)
67              tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
68          panic("writing to TICK compare register %#X\n", val);
69          break;
70
71        case MISCREG_STICK_CMPR:
72          if (sTickCompare == NULL)
73              sTickCompare = new STickCompareEvent(this, tc);
74          setReg(miscReg, val);
75          if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
76                  sTickCompare->deschedule();
77          time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
78             tc->getCpuPtr()->instCount();
79          if (!(stick_cmpr & ~mask(63)) && time > 0)
80              sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
81          DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
82          break;
83
84        case MISCREG_PSTATE:
85          if (val & ie && !(pstate & ie)) {
86              tc->getCpuPtr()->checkInterrupts = true;
87          }
88          setReg(miscReg, val);
89
90        case MISCREG_PIL:
91          if (val < pil) {
92              tc->getCpuPtr()->checkInterrupts = true;
93          }
94          setReg(miscReg, val);
95          break;
96
97        case MISCREG_HVER:
98          panic("Shouldn't be writing HVER\n");
99
100        case MISCREG_HTBA:
101          // clear lower 7 bits on writes.
102          setReg(miscReg, val & ULL(~0x7FFF));
103          break;
104
105        case MISCREG_QUEUE_CPU_MONDO_HEAD:
106        case MISCREG_QUEUE_CPU_MONDO_TAIL:
107        case MISCREG_QUEUE_DEV_MONDO_HEAD:
108        case MISCREG_QUEUE_DEV_MONDO_TAIL:
109        case MISCREG_QUEUE_RES_ERROR_HEAD:
110        case MISCREG_QUEUE_RES_ERROR_TAIL:
111        case MISCREG_QUEUE_NRES_ERROR_HEAD:
112        case MISCREG_QUEUE_NRES_ERROR_TAIL:
113          setReg(miscReg, val);
114          tc->getCpuPtr()->checkInterrupts = true;
115          break;
116
117        case MISCREG_HSTICK_CMPR:
118          if (hSTickCompare == NULL)
119              hSTickCompare = new HSTickCompareEvent(this, tc);
120          setReg(miscReg, val);
121          if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
122                hSTickCompare->deschedule();
123          time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
124             tc->getCpuPtr()->instCount();
125          if (!(hstick_cmpr & ~mask(63)) && time > 0)
126              hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
127          DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
128          break;
129
130        case MISCREG_HPSTATE:
131          // T1000 spec says impl. dependent val must always be 1
132          setReg(miscReg, val | id);
133          break;
134        case MISCREG_HTSTATE:
135        case MISCREG_STRAND_STS_REG:
136          setReg(miscReg, val);
137          break;
138
139        default:
140          panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
141    }
142}
143
144MiscReg
145MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
146{
147    switch (miscReg) {
148      /* Privileged registers. */
149      case MISCREG_QUEUE_CPU_MONDO_HEAD:
150      case MISCREG_QUEUE_CPU_MONDO_TAIL:
151      case MISCREG_QUEUE_DEV_MONDO_HEAD:
152      case MISCREG_QUEUE_DEV_MONDO_TAIL:
153      case MISCREG_QUEUE_RES_ERROR_HEAD:
154      case MISCREG_QUEUE_RES_ERROR_TAIL:
155      case MISCREG_QUEUE_NRES_ERROR_HEAD:
156      case MISCREG_QUEUE_NRES_ERROR_TAIL:
157      case MISCREG_SOFTINT:
158      case MISCREG_TICK_CMPR:
159      case MISCREG_STICK_CMPR:
160      case MISCREG_PIL:
161      case MISCREG_HPSTATE:
162      case MISCREG_HINTP:
163      case MISCREG_HTSTATE:
164      case MISCREG_STRAND_STS_REG:
165      case MISCREG_HSTICK_CMPR:
166        return readReg(miscReg) ;
167
168      case MISCREG_HTBA:
169        return readReg(miscReg) & ULL(~0x7FFF);
170      case MISCREG_HVER:
171        return NWindows | MaxTL << 8 | MaxGL << 16;
172
173      default:
174        panic("Invalid read to FS misc register\n");
175    }
176}
177/*
178        In Niagra STICK==TICK so this isn't needed
179        case MISCREG_STICK:
180          SparcSystem *sys;
181          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
182          assert(sys != NULL);
183          return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
184*/
185
186
187
188void
189MiscRegFile::processTickCompare(ThreadContext *tc)
190{
191    panic("tick compare not implemented\n");
192}
193
194void
195MiscRegFile::processSTickCompare(ThreadContext *tc)
196{
197    // since our microcode instructions take two cycles we need to check if
198    // we're actually at the correct cycle or we need to wait a little while
199    // more
200    int ticks;
201    ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
202            tc->getCpuPtr()->instCount();
203    assert(ticks >= 0 && "stick compare missed interrupt cycle");
204
205    if (ticks == 0) {
206        DPRINTF(Timer, "STick compare cycle reached at %#x\n",
207                (stick_cmpr & mask(63)));
208        tc->getCpuPtr()->checkInterrupts = true;
209        softint |= ULL(1) << 16;
210    } else
211        sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
212}
213
214void
215MiscRegFile::processHSTickCompare(ThreadContext *tc)
216{
217    // since our microcode instructions take two cycles we need to check if
218    // we're actually at the correct cycle or we need to wait a little while
219    // more
220    int ticks;
221    ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
222            tc->getCpuPtr()->instCount();
223    assert(ticks >= 0 && "hstick compare missed interrupt cycle");
224
225    if (ticks == 0) {
226        DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
227                (stick_cmpr & mask(63)));
228        tc->getCpuPtr()->checkInterrupts = true;
229        // Need to do something to cause interrupt to happen here !!! @todo
230    } else
231        sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
232}
233
234