ua2005.cc revision 3897:d7eee8c8215c 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/miscregfile.hh"
30#include "base/bitfield.hh"
31#include "base/trace.hh"
32#include "cpu/base.hh"
33#include "cpu/thread_context.hh"
34
35using namespace SparcISA;
36
37void
38MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
39                                ThreadContext *tc)
40{
41    int64_t time;
42    switch (miscReg) {
43        /* Full system only ASRs */
44      case MISCREG_SOFTINT:
45        // Check if we are going to interrupt because of something
46        setReg(miscReg, val);
47        tc->getCpuPtr()->post_interrupt(soft_interrupt);
48        warn("Writing to softint not really supported, writing: %#x\n", val);
49        break;
50
51      case MISCREG_SOFTINT_CLR:
52        return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
53      case MISCREG_SOFTINT_SET:
54        return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
55
56      case MISCREG_TICK_CMPR:
57        if (tickCompare == NULL)
58            tickCompare = new TickCompareEvent(this, tc);
59        setReg(miscReg, val);
60        if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
61            tickCompare->deschedule();
62        time = (tick_cmpr & mask(63)) - (tick & mask(63));
63        if (!(tick_cmpr & ~mask(63)) && time > 0)
64            tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
65        panic("writing to TICK compare register %#X\n", val);
66        break;
67
68      case MISCREG_STICK_CMPR:
69        if (sTickCompare == NULL)
70            sTickCompare = new STickCompareEvent(this, tc);
71        setReg(miscReg, val);
72        if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
73            sTickCompare->deschedule();
74        time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
75            tc->getCpuPtr()->instCount();
76        if (!(stick_cmpr & ~mask(63)) && time > 0)
77            sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
78        DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
79        break;
80
81      case MISCREG_PSTATE:
82        if (val & PSTATE::ie && !(pstate & PSTATE::ie)) {
83            tc->getCpuPtr()->checkInterrupts = true;
84        }
85        setReg(miscReg, val);
86
87      case MISCREG_PIL:
88        if (val < pil) {
89            tc->getCpuPtr()->checkInterrupts = true;
90        }
91        setReg(miscReg, val);
92        break;
93
94      case MISCREG_HVER:
95        panic("Shouldn't be writing HVER\n");
96
97      case MISCREG_HTBA:
98        // clear lower 7 bits on writes.
99        setReg(miscReg, val & ULL(~0x7FFF));
100        break;
101
102      case MISCREG_QUEUE_CPU_MONDO_HEAD:
103      case MISCREG_QUEUE_CPU_MONDO_TAIL:
104      case MISCREG_QUEUE_DEV_MONDO_HEAD:
105      case MISCREG_QUEUE_DEV_MONDO_TAIL:
106      case MISCREG_QUEUE_RES_ERROR_HEAD:
107      case MISCREG_QUEUE_RES_ERROR_TAIL:
108      case MISCREG_QUEUE_NRES_ERROR_HEAD:
109      case MISCREG_QUEUE_NRES_ERROR_TAIL:
110        setReg(miscReg, val);
111        tc->getCpuPtr()->checkInterrupts = true;
112        break;
113
114      case MISCREG_HSTICK_CMPR:
115        if (hSTickCompare == NULL)
116            hSTickCompare = new HSTickCompareEvent(this, tc);
117        setReg(miscReg, val);
118        if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
119            hSTickCompare->deschedule();
120        time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
121            tc->getCpuPtr()->instCount();
122        if (!(hstick_cmpr & ~mask(63)) && time > 0)
123            hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
124        DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
125        break;
126
127      case MISCREG_HPSTATE:
128        // T1000 spec says impl. dependent val must always be 1
129        setReg(miscReg, val | HPSTATE::id);
130        break;
131      case MISCREG_HTSTATE:
132      case MISCREG_STRAND_STS_REG:
133        setReg(miscReg, val);
134        break;
135
136      default:
137        panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
138    }
139}
140
141MiscReg
142MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
143{
144    switch (miscReg) {
145        /* Privileged registers. */
146      case MISCREG_QUEUE_CPU_MONDO_HEAD:
147      case MISCREG_QUEUE_CPU_MONDO_TAIL:
148      case MISCREG_QUEUE_DEV_MONDO_HEAD:
149      case MISCREG_QUEUE_DEV_MONDO_TAIL:
150      case MISCREG_QUEUE_RES_ERROR_HEAD:
151      case MISCREG_QUEUE_RES_ERROR_TAIL:
152      case MISCREG_QUEUE_NRES_ERROR_HEAD:
153      case MISCREG_QUEUE_NRES_ERROR_TAIL:
154      case MISCREG_SOFTINT:
155      case MISCREG_TICK_CMPR:
156      case MISCREG_STICK_CMPR:
157      case MISCREG_PIL:
158      case MISCREG_HPSTATE:
159      case MISCREG_HINTP:
160      case MISCREG_HTSTATE:
161      case MISCREG_STRAND_STS_REG:
162      case MISCREG_HSTICK_CMPR:
163        return readReg(miscReg) ;
164
165      case MISCREG_HTBA:
166        return readReg(miscReg) & ULL(~0x7FFF);
167      case MISCREG_HVER:
168        return NWindows | MaxTL << 8 | MaxGL << 16;
169
170      default:
171        panic("Invalid read to FS misc register\n");
172    }
173}
174/*
175  In Niagra STICK==TICK so this isn't needed
176  case MISCREG_STICK:
177  SparcSystem *sys;
178  sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
179  assert(sys != NULL);
180  return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
181*/
182
183
184
185void
186MiscRegFile::processTickCompare(ThreadContext *tc)
187{
188    panic("tick compare not implemented\n");
189}
190
191void
192MiscRegFile::processSTickCompare(ThreadContext *tc)
193{
194    // since our microcode instructions take two cycles we need to check if
195    // we're actually at the correct cycle or we need to wait a little while
196    // more
197    int ticks;
198    ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
199        tc->getCpuPtr()->instCount();
200    assert(ticks >= 0 && "stick compare missed interrupt cycle");
201
202    if (ticks == 0) {
203        DPRINTF(Timer, "STick compare cycle reached at %#x\n",
204                (stick_cmpr & mask(63)));
205        tc->getCpuPtr()->post_interrupt(soft_interrupt);
206        tc->getCpuPtr()->checkInterrupts = true;
207        softint |= ULL(1) << 16;
208    } else
209        sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
210}
211
212void
213MiscRegFile::processHSTickCompare(ThreadContext *tc)
214{
215    // since our microcode instructions take two cycles we need to check if
216    // we're actually at the correct cycle or we need to wait a little while
217    // more
218    int ticks;
219    ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
220        tc->getCpuPtr()->instCount();
221    assert(ticks >= 0 && "hstick compare missed interrupt cycle");
222
223    if (ticks == 0) {
224        DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
225                (stick_cmpr & mask(63)));
226        tc->getCpuPtr()->post_interrupt(hstick_match);
227        tc->getCpuPtr()->checkInterrupts = true;
228        // Need to do something to cause interrupt to happen here !!! @todo
229    } else
230        sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
231}
232
233