ua2005.cc revision 3828:9444f62adb12 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/miscregfile.hh"
32#include "base/bitfield.hh"
33#include "base/trace.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36
37using namespace SparcISA;
38
39void
40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
41        ThreadContext *tc)
42{
43    int64_t time;
44    switch (miscReg) {
45        /* Full system only ASRs */
46        case MISCREG_SOFTINT:
47          // Check if we are going to interrupt because of something
48          setReg(miscReg, val);
49          tc->getCpuPtr()->checkInterrupts = true;
50          warn("Writing to softint not really supported, writing: %#x\n", val);
51          break;
52
53        case MISCREG_SOFTINT_CLR:
54          return setRegWithEffect(miscReg, ~val & softint, tc);
55        case MISCREG_SOFTINT_SET:
56          return setRegWithEffect(miscReg, val | softint, tc);
57
58        case MISCREG_TICK_CMPR:
59          if (tickCompare == NULL)
60              tickCompare = new TickCompareEvent(this, tc);
61          setReg(miscReg, val);
62          if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
63                  tickCompare->deschedule();
64          time = (tick_cmpr & mask(63)) - (tick & mask(63));
65          if (!(tick_cmpr & ~mask(63)) && time > 0)
66              tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
67          warn ("writing to TICK compare register %#X\n", val);
68          break;
69
70        case MISCREG_STICK_CMPR:
71          if (sTickCompare == NULL)
72              sTickCompare = new STickCompareEvent(this, tc);
73          setReg(miscReg, val);
74          if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
75                  sTickCompare->deschedule();
76          time = (stick_cmpr & mask(63)) - (stick & mask(63));
77          if (!(stick_cmpr & ~mask(63)) && time > 0)
78              sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
79          warn ("writing to sTICK compare register value %#X\n", val);
80          break;
81
82        case MISCREG_PSTATE:
83          if (val & ie && !(pstate & ie)) {
84              tc->getCpuPtr()->checkInterrupts = true;
85          }
86          setReg(miscReg, val);
87
88        case MISCREG_PIL:
89          if (val < pil) {
90              tc->getCpuPtr()->checkInterrupts = true;
91          }
92          setReg(miscReg, val);
93          break;
94
95        case MISCREG_HVER:
96          panic("Shouldn't be writing HVER\n");
97
98        case MISCREG_HTBA:
99          // clear lower 7 bits on writes.
100          setReg(miscReg, val & ULL(~0x7FFF));
101          break;
102
103        case MISCREG_QUEUE_CPU_MONDO_HEAD:
104        case MISCREG_QUEUE_CPU_MONDO_TAIL:
105        case MISCREG_QUEUE_DEV_MONDO_HEAD:
106        case MISCREG_QUEUE_DEV_MONDO_TAIL:
107        case MISCREG_QUEUE_RES_ERROR_HEAD:
108        case MISCREG_QUEUE_RES_ERROR_TAIL:
109        case MISCREG_QUEUE_NRES_ERROR_HEAD:
110        case MISCREG_QUEUE_NRES_ERROR_TAIL:
111          setReg(miscReg, val);
112          tc->getCpuPtr()->checkInterrupts = true;
113          break;
114
115        case MISCREG_HSTICK_CMPR:
116          if (hSTickCompare == NULL)
117              hSTickCompare = new HSTickCompareEvent(this, tc);
118          setReg(miscReg, val);
119          if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
120                hSTickCompare->deschedule();
121          time = (hstick_cmpr & mask(63)) - (stick & mask(63));
122          if (!(hstick_cmpr & ~mask(63)) && time > 0)
123              hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
124          warn ("writing to hsTICK compare register value %#X\n", val);
125          break;
126
127        case MISCREG_HPSTATE:
128          // T1000 spec says impl. dependent val must always be 1
129          setReg(miscReg, val | id);
130
131        case MISCREG_HTSTATE:
132        case MISCREG_STRAND_STS_REG:
133          setReg(miscReg, val);
134          break;
135
136        default:
137          panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
138    }
139}
140
141MiscReg
142MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
143{
144    switch (miscReg) {
145      /* Privileged registers. */
146      case MISCREG_QUEUE_CPU_MONDO_HEAD:
147      case MISCREG_QUEUE_CPU_MONDO_TAIL:
148      case MISCREG_QUEUE_DEV_MONDO_HEAD:
149      case MISCREG_QUEUE_DEV_MONDO_TAIL:
150      case MISCREG_QUEUE_RES_ERROR_HEAD:
151      case MISCREG_QUEUE_RES_ERROR_TAIL:
152      case MISCREG_QUEUE_NRES_ERROR_HEAD:
153      case MISCREG_QUEUE_NRES_ERROR_TAIL:
154      case MISCREG_SOFTINT:
155      case MISCREG_TICK_CMPR:
156      case MISCREG_STICK_CMPR:
157      case MISCREG_PIL:
158      case MISCREG_HPSTATE:
159      case MISCREG_HINTP:
160      case MISCREG_HTSTATE:
161      case MISCREG_STRAND_STS_REG:
162      case MISCREG_HSTICK_CMPR:
163        return readReg(miscReg) ;
164
165      case MISCREG_HTBA:
166        return readReg(miscReg) & ULL(~0x7FFF);
167      case MISCREG_HVER:
168        return NWindows | MaxTL << 8 | MaxGL << 16;
169
170      default:
171        panic("Invalid read to FS misc register\n");
172    }
173}
174/*
175        In Niagra STICK==TICK so this isn't needed
176        case MISCREG_STICK:
177          SparcSystem *sys;
178          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
179          assert(sys != NULL);
180          return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
181*/
182
183
184
185void
186MiscRegFile::processTickCompare(ThreadContext *tc)
187{
188    panic("tick compare not implemented\n");
189}
190
191void
192MiscRegFile::processSTickCompare(ThreadContext *tc)
193{
194    panic("tick compare not implemented\n");
195}
196
197void
198MiscRegFile::processHSTickCompare(ThreadContext *tc)
199{
200    panic("tick compare not implemented\n");
201}
202
203