ua2005.cc revision 3825:9b5e6c4d3ecb
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include "arch/sparc/miscregfile.hh" 32#include "base/bitfield.hh" 33#include "base/trace.hh" 34#include "cpu/base.hh" 35#include "cpu/thread_context.hh" 36 37using namespace SparcISA; 38 39void 40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 41 ThreadContext *tc) 42{ 43 int64_t time; 44 int oldLevel, newLevel; 45 switch (miscReg) { 46 /* Full system only ASRs */ 47 case MISCREG_SOFTINT: 48 // Check if we are going to interrupt because of something 49 oldLevel = InterruptLevel(softint); 50 newLevel = InterruptLevel(val); 51 setReg(miscReg, val); 52 //if (newLevel > oldLevel) 53 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 54 //tc->getCpuPtr()->checkInterrupts = true; 55 //panic("SOFTINT not implemented\n"); 56 warn("Writing to softint not really supported, writing: %#x\n", val); 57 break; 58 59 case MISCREG_SOFTINT_CLR: 60 return setRegWithEffect(miscReg, ~val & softint, tc); 61 case MISCREG_SOFTINT_SET: 62 return setRegWithEffect(miscReg, val | softint, tc); 63 64 case MISCREG_TICK_CMPR: 65 if (tickCompare == NULL) 66 tickCompare = new TickCompareEvent(this, tc); 67 setReg(miscReg, val); 68 if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 69 tickCompare->deschedule(); 70 time = (tick_cmpr & mask(63)) - (tick & mask(63)); 71 if (!(tick_cmpr & ~mask(63)) && time > 0) 72 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 73 warn ("writing to TICK compare register %#X\n", val); 74 break; 75 76 case MISCREG_STICK_CMPR: 77 if (sTickCompare == NULL) 78 sTickCompare = new STickCompareEvent(this, tc); 79 setReg(miscReg, val); 80 if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) 81 sTickCompare->deschedule(); 82 time = (stick_cmpr & mask(63)) - (stick & mask(63)); 83 if (!(stick_cmpr & ~mask(63)) && time > 0) 84 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 85 warn ("writing to sTICK compare register value %#X\n", val); 86 break; 87 88 case MISCREG_PIL: 89 setReg(miscReg, val); 90 //tc->getCpuPtr()->checkInterrupts; 91 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 92 // panic("PIL not implemented\n"); 93 warn ("PIL not implemented writing %#X\n", val); 94 break; 95 96 case MISCREG_HVER: 97 panic("Shouldn't be writing HVER\n"); 98 99 case MISCREG_HTBA: 100 // clear lower 7 bits on writes. 101 setReg(miscReg, val & ULL(~0x7FFF)); 102 break; 103 104 case MISCREG_QUEUE_CPU_MONDO_HEAD: 105 case MISCREG_QUEUE_CPU_MONDO_TAIL: 106 case MISCREG_QUEUE_DEV_MONDO_HEAD: 107 case MISCREG_QUEUE_DEV_MONDO_TAIL: 108 case MISCREG_QUEUE_RES_ERROR_HEAD: 109 case MISCREG_QUEUE_RES_ERROR_TAIL: 110 case MISCREG_QUEUE_NRES_ERROR_HEAD: 111 case MISCREG_QUEUE_NRES_ERROR_TAIL: 112 setReg(miscReg, val); 113 tc->getCpuPtr()->checkInterrupts = true; 114 break; 115 116 case MISCREG_HSTICK_CMPR: 117 if (hSTickCompare == NULL) 118 hSTickCompare = new HSTickCompareEvent(this, tc); 119 setReg(miscReg, val); 120 if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) 121 hSTickCompare->deschedule(); 122 time = (hstick_cmpr & mask(63)) - (stick & mask(63)); 123 if (!(hstick_cmpr & ~mask(63)) && time > 0) 124 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 125 warn ("writing to hsTICK compare register value %#X\n", val); 126 break; 127 128 case MISCREG_HPSTATE: 129 // i.d. is always set on any hpstate write 130 setReg(miscReg, val | 1 << 11); 131 break; 132 case MISCREG_HTSTATE: 133 case MISCREG_STRAND_STS_REG: 134 setReg(miscReg, val); 135 break; 136 137 default: 138 panic("Invalid write to FS misc register\n"); 139 } 140} 141 142MiscReg 143MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 144{ 145 switch (miscReg) { 146 /* Privileged registers. */ 147 case MISCREG_QUEUE_CPU_MONDO_HEAD: 148 case MISCREG_QUEUE_CPU_MONDO_TAIL: 149 case MISCREG_QUEUE_DEV_MONDO_HEAD: 150 case MISCREG_QUEUE_DEV_MONDO_TAIL: 151 case MISCREG_QUEUE_RES_ERROR_HEAD: 152 case MISCREG_QUEUE_RES_ERROR_TAIL: 153 case MISCREG_QUEUE_NRES_ERROR_HEAD: 154 case MISCREG_QUEUE_NRES_ERROR_TAIL: 155 case MISCREG_SOFTINT: 156 case MISCREG_TICK_CMPR: 157 case MISCREG_STICK_CMPR: 158 case MISCREG_PIL: 159 case MISCREG_HPSTATE: 160 case MISCREG_HINTP: 161 case MISCREG_HTSTATE: 162 case MISCREG_STRAND_STS_REG: 163 case MISCREG_HSTICK_CMPR: 164 return readReg(miscReg) ; 165 166 case MISCREG_HTBA: 167 return readReg(miscReg) & ULL(~0x7FFF); 168 case MISCREG_HVER: 169 return NWindows | MaxTL << 8 | MaxGL << 16; 170 171 default: 172 panic("Invalid read to FS misc register\n"); 173 } 174} 175/* 176 In Niagra STICK==TICK so this isn't needed 177 case MISCREG_STICK: 178 SparcSystem *sys; 179 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 180 assert(sys != NULL); 181 return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 182*/ 183 184 185 186void 187MiscRegFile::processTickCompare(ThreadContext *tc) 188{ 189 panic("tick compare not implemented\n"); 190} 191 192void 193MiscRegFile::processSTickCompare(ThreadContext *tc) 194{ 195 panic("tick compare not implemented\n"); 196} 197 198void 199MiscRegFile::processHSTickCompare(ThreadContext *tc) 200{ 201 panic("tick compare not implemented\n"); 202} 203 204