tlb.hh revision 8888:befcf4d79fc1 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
37#include "mem/request.hh"
38#include "params/SparcTLB.hh"
39#include "sim/fault_fwd.hh"
40#include "sim/tlb.hh"
41
42class ThreadContext;
43class Packet;
44
45namespace SparcISA
46{
47
48class TLB : public BaseTLB
49{
50    // These faults need to be able to populate the tlb in SE mode.
51    friend class FastInstructionAccessMMUMiss;
52    friend class FastDataAccessMMUMiss;
53
54    // TLB state
55  protected:
56    // Only used when this is the data TLB.
57    uint64_t sfar;
58    uint64_t c0_tsb_ps0;
59    uint64_t c0_tsb_ps1;
60    uint64_t c0_config;
61    uint64_t cx_tsb_ps0;
62    uint64_t cx_tsb_ps1;
63    uint64_t cx_config;
64    uint64_t sfsr;
65    uint64_t tag_access;
66
67  protected:
68    TlbMap lookupTable;;
69    typedef TlbMap::iterator MapIter;
70
71    TlbEntry *tlb;
72
73    int size;
74    int usedEntries;
75    int lastReplaced;
76
77    uint64_t cacheState;
78    bool cacheValid;
79
80    std::list<TlbEntry*> freeList;
81
82    enum FaultTypes {
83        OtherFault = 0,
84        PrivViolation = 0x1,
85        SideEffect = 0x2,
86        AtomicToIo = 0x4,
87        IllegalAsi = 0x8,
88        LoadFromNfo = 0x10,
89        VaOutOfRange = 0x20,
90        VaOutOfRangeJmp = 0x40
91    };
92
93    enum ContextType {
94        Primary = 0,
95        Secondary = 1,
96        Nucleus = 2
97    };
98
99    enum TsbPageSize {
100        Ps0,
101        Ps1
102    };
103  public:
104    /** lookup an entry in the TLB based on the partition id, and real bit if
105     * real is true or the partition id, and context id if real is false.
106     * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
107     * @param paritition_id partition this entry is for
108     * @param real is this a real->phys or virt->phys translation
109     * @param context_id if this is virt->phys what context
110     * @param update_used should ew update the used bits in the
111     * entries on not useful if we are trying to do a va->pa without
112     * mucking with any state for a debug read for example.
113     * @return A pointer to a tlb entry
114     */
115    TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
116            bool update_used = true);
117  protected:
118    /** Insert a PTE into the TLB. */
119    void insert(Addr vpn, int partition_id, int context_id, bool real,
120            const PageTableEntry& PTE, int entry = -1);
121
122    /** Given an entry id, read that tlb entries' tag. */
123    uint64_t TagRead(int entry);
124
125    /** Remove all entries from the TLB */
126    void invalidateAll();
127
128    /** Remove all non-locked entries from the tlb that match partition id. */
129    void demapAll(int partition_id);
130
131    /** Remove all entries that match a given context/partition id. */
132    void demapContext(int partition_id, int context_id);
133
134    /** Remve all entries that match a certain partition id, (contextid), and
135     * va). */
136    void demapPage(Addr va, int partition_id, bool real, int context_id);
137
138    /** Checks if the virtual address provided is a valid one. */
139    bool validVirtualAddress(Addr va, bool am);
140
141    void writeSfsr(bool write, ContextType ct,
142            bool se, FaultTypes ft, int asi);
143
144    void clearUsedBits();
145
146
147    void writeTagAccess(Addr va, int context);
148
149    Fault translateInst(RequestPtr req, ThreadContext *tc);
150    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
151
152  public:
153    typedef SparcTLBParams Params;
154    TLB(const Params *p);
155
156    void
157    demapPage(Addr vaddr, uint64_t asn)
158    {
159        panic("demapPage(Addr) is not implemented.\n");
160    }
161
162    void dumpAll();
163
164    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
165    void translateTiming(RequestPtr req, ThreadContext *tc,
166            Translation *translation, Mode mode);
167    /** Stub function for compilation support with CheckerCPU. SPARC ISA
168     *  does not support the Checker model at the moment
169     */
170    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
171    Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
172    Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
173    void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
174
175    // Checkpointing
176    virtual void serialize(std::ostream &os);
177    virtual void unserialize(Checkpoint *cp, const std::string &section);
178
179    /** Give an entry id, read that tlb entries' tte */
180    uint64_t TteRead(int entry);
181
182  private:
183    void writeSfsr(Addr a, bool write, ContextType ct,
184            bool se, FaultTypes ft, int asi);
185
186    uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
187        uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
188
189
190    TlbEntry *cacheEntry[2];
191    ASI cacheAsi[2];
192};
193
194}
195
196#endif // __ARCH_SPARC_TLB_HH__
197