tlb.hh revision 8749:ca2ae1194e11
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#ifndef __ARCH_SPARC_TLB_HH__ 32#define __ARCH_SPARC_TLB_HH__ 33 34#include "arch/sparc/asi.hh" 35#include "arch/sparc/tlb_map.hh" 36#include "base/misc.hh" 37#include "config/full_system.hh" 38#include "mem/request.hh" 39#include "params/SparcTLB.hh" 40#include "sim/fault_fwd.hh" 41#include "sim/tlb.hh" 42 43class ThreadContext; 44class Packet; 45 46namespace SparcISA 47{ 48 49class TLB : public BaseTLB 50{ 51 // These faults need to be able to populate the tlb in SE mode. 52 friend class FastInstructionAccessMMUMiss; 53 friend class FastDataAccessMMUMiss; 54 55 // TLB state 56 protected: 57 // Only used when this is the data TLB. 58 uint64_t sfar; 59 uint64_t c0_tsb_ps0; 60 uint64_t c0_tsb_ps1; 61 uint64_t c0_config; 62 uint64_t cx_tsb_ps0; 63 uint64_t cx_tsb_ps1; 64 uint64_t cx_config; 65 uint64_t sfsr; 66 uint64_t tag_access; 67 68 protected: 69 TlbMap lookupTable;; 70 typedef TlbMap::iterator MapIter; 71 72 TlbEntry *tlb; 73 74 int size; 75 int usedEntries; 76 int lastReplaced; 77 78 uint64_t cacheState; 79 bool cacheValid; 80 81 std::list<TlbEntry*> freeList; 82 83 enum FaultTypes { 84 OtherFault = 0, 85 PrivViolation = 0x1, 86 SideEffect = 0x2, 87 AtomicToIo = 0x4, 88 IllegalAsi = 0x8, 89 LoadFromNfo = 0x10, 90 VaOutOfRange = 0x20, 91 VaOutOfRangeJmp = 0x40 92 }; 93 94 enum ContextType { 95 Primary = 0, 96 Secondary = 1, 97 Nucleus = 2 98 }; 99 100 enum TsbPageSize { 101 Ps0, 102 Ps1 103 }; 104 public: 105 /** lookup an entry in the TLB based on the partition id, and real bit if 106 * real is true or the partition id, and context id if real is false. 107 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0) 108 * @param paritition_id partition this entry is for 109 * @param real is this a real->phys or virt->phys translation 110 * @param context_id if this is virt->phys what context 111 * @param update_used should ew update the used bits in the 112 * entries on not useful if we are trying to do a va->pa without 113 * mucking with any state for a debug read for example. 114 * @return A pointer to a tlb entry 115 */ 116 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0, 117 bool update_used = true); 118 protected: 119 /** Insert a PTE into the TLB. */ 120 void insert(Addr vpn, int partition_id, int context_id, bool real, 121 const PageTableEntry& PTE, int entry = -1); 122 123 /** Given an entry id, read that tlb entries' tag. */ 124 uint64_t TagRead(int entry); 125 126 /** Remove all entries from the TLB */ 127 void invalidateAll(); 128 129 /** Remove all non-locked entries from the tlb that match partition id. */ 130 void demapAll(int partition_id); 131 132 /** Remove all entries that match a given context/partition id. */ 133 void demapContext(int partition_id, int context_id); 134 135 /** Remve all entries that match a certain partition id, (contextid), and 136 * va). */ 137 void demapPage(Addr va, int partition_id, bool real, int context_id); 138 139 /** Checks if the virtual address provided is a valid one. */ 140 bool validVirtualAddress(Addr va, bool am); 141 142 void writeSfsr(bool write, ContextType ct, 143 bool se, FaultTypes ft, int asi); 144 145 void clearUsedBits(); 146 147 148 void writeTagAccess(Addr va, int context); 149 150 Fault translateInst(RequestPtr req, ThreadContext *tc); 151 Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 152 153 public: 154 typedef SparcTLBParams Params; 155 TLB(const Params *p); 156 157 void 158 demapPage(Addr vaddr, uint64_t asn) 159 { 160 panic("demapPage(Addr) is not implemented.\n"); 161 } 162 163 void dumpAll(); 164 165 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 166 void translateTiming(RequestPtr req, ThreadContext *tc, 167 Translation *translation, Mode mode); 168 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); 169 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); 170 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); 171 172 // Checkpointing 173 virtual void serialize(std::ostream &os); 174 virtual void unserialize(Checkpoint *cp, const std::string §ion); 175 176 /** Give an entry id, read that tlb entries' tte */ 177 uint64_t TteRead(int entry); 178 179 private: 180 void writeSfsr(Addr a, bool write, ContextType ct, 181 bool se, FaultTypes ft, int asi); 182 183 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 184 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config); 185 186 187 TlbEntry *cacheEntry[2]; 188 ASI cacheAsi[2]; 189}; 190 191} 192 193#endif // __ARCH_SPARC_TLB_HH__ 194