tlb.hh revision 8748:01be402c5bf1
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#ifndef __ARCH_SPARC_TLB_HH__ 32#define __ARCH_SPARC_TLB_HH__ 33 34#include "arch/sparc/asi.hh" 35#include "arch/sparc/tlb_map.hh" 36#include "base/misc.hh" 37#include "config/full_system.hh" 38#include "mem/request.hh" 39#include "params/SparcTLB.hh" 40#include "sim/fault_fwd.hh" 41#include "sim/tlb.hh" 42 43class ThreadContext; 44class Packet; 45 46namespace SparcISA 47{ 48 49class TLB : public BaseTLB 50{ 51#if !FULL_SYSTEM 52 // These faults need to be able to populate the tlb in SE mode. 53 friend class FastInstructionAccessMMUMiss; 54 friend class FastDataAccessMMUMiss; 55#endif 56 57 // TLB state 58 protected: 59 // Only used when this is the data TLB. 60 uint64_t sfar; 61 uint64_t c0_tsb_ps0; 62 uint64_t c0_tsb_ps1; 63 uint64_t c0_config; 64 uint64_t cx_tsb_ps0; 65 uint64_t cx_tsb_ps1; 66 uint64_t cx_config; 67 uint64_t sfsr; 68 uint64_t tag_access; 69 70 protected: 71 TlbMap lookupTable;; 72 typedef TlbMap::iterator MapIter; 73 74 TlbEntry *tlb; 75 76 int size; 77 int usedEntries; 78 int lastReplaced; 79 80 uint64_t cacheState; 81 bool cacheValid; 82 83 std::list<TlbEntry*> freeList; 84 85 enum FaultTypes { 86 OtherFault = 0, 87 PrivViolation = 0x1, 88 SideEffect = 0x2, 89 AtomicToIo = 0x4, 90 IllegalAsi = 0x8, 91 LoadFromNfo = 0x10, 92 VaOutOfRange = 0x20, 93 VaOutOfRangeJmp = 0x40 94 }; 95 96 enum ContextType { 97 Primary = 0, 98 Secondary = 1, 99 Nucleus = 2 100 }; 101 102 enum TsbPageSize { 103 Ps0, 104 Ps1 105 }; 106 public: 107 /** lookup an entry in the TLB based on the partition id, and real bit if 108 * real is true or the partition id, and context id if real is false. 109 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0) 110 * @param paritition_id partition this entry is for 111 * @param real is this a real->phys or virt->phys translation 112 * @param context_id if this is virt->phys what context 113 * @param update_used should ew update the used bits in the 114 * entries on not useful if we are trying to do a va->pa without 115 * mucking with any state for a debug read for example. 116 * @return A pointer to a tlb entry 117 */ 118 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0, 119 bool update_used = true); 120 protected: 121 /** Insert a PTE into the TLB. */ 122 void insert(Addr vpn, int partition_id, int context_id, bool real, 123 const PageTableEntry& PTE, int entry = -1); 124 125 /** Given an entry id, read that tlb entries' tag. */ 126 uint64_t TagRead(int entry); 127 128 /** Remove all entries from the TLB */ 129 void invalidateAll(); 130 131 /** Remove all non-locked entries from the tlb that match partition id. */ 132 void demapAll(int partition_id); 133 134 /** Remove all entries that match a given context/partition id. */ 135 void demapContext(int partition_id, int context_id); 136 137 /** Remve all entries that match a certain partition id, (contextid), and 138 * va). */ 139 void demapPage(Addr va, int partition_id, bool real, int context_id); 140 141 /** Checks if the virtual address provided is a valid one. */ 142 bool validVirtualAddress(Addr va, bool am); 143 144 void writeSfsr(bool write, ContextType ct, 145 bool se, FaultTypes ft, int asi); 146 147 void clearUsedBits(); 148 149 150 void writeTagAccess(Addr va, int context); 151 152 Fault translateInst(RequestPtr req, ThreadContext *tc); 153 Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 154 155 public: 156 typedef SparcTLBParams Params; 157 TLB(const Params *p); 158 159 void 160 demapPage(Addr vaddr, uint64_t asn) 161 { 162 panic("demapPage(Addr) is not implemented.\n"); 163 } 164 165 void dumpAll(); 166 167 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 168 void translateTiming(RequestPtr req, ThreadContext *tc, 169 Translation *translation, Mode mode); 170 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); 171 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); 172 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); 173 174 // Checkpointing 175 virtual void serialize(std::ostream &os); 176 virtual void unserialize(Checkpoint *cp, const std::string §ion); 177 178 /** Give an entry id, read that tlb entries' tte */ 179 uint64_t TteRead(int entry); 180 181 private: 182 void writeSfsr(Addr a, bool write, ContextType ct, 183 bool se, FaultTypes ft, int asi); 184 185 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 186 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config); 187 188 189 TlbEntry *cacheEntry[2]; 190 ASI cacheAsi[2]; 191}; 192 193} 194 195#endif // __ARCH_SPARC_TLB_HH__ 196