tlb.hh revision 3806:65ae5388c059 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/tlb_map.hh"
35#include "base/misc.hh"
36#include "mem/request.hh"
37#include "sim/faults.hh"
38#include "sim/sim_object.hh"
39
40class ThreadContext;
41class Packet;
42
43namespace SparcISA
44{
45
46class TLB : public SimObject
47{
48  protected:
49    TlbMap lookupTable;;
50    typedef TlbMap::iterator MapIter;
51
52    TlbEntry *tlb;
53
54    int size;
55    int usedEntries;
56
57    enum FaultTypes {
58        OtherFault = 0,
59        PrivViolation = 0x1,
60        SideEffect = 0x2,
61        AtomicToIo = 0x4,
62        IllegalAsi = 0x8,
63        LoadFromNfo = 0x10,
64        VaOutOfRange = 0x20,
65        VaOutOfRangeJmp = 0x40
66    };
67
68    enum ContextType {
69        Primary = 0,
70        Secondary = 1,
71        Nucleus = 2
72    };
73
74
75    /** lookup an entry in the TLB based on the partition id, and real bit if
76     * real is true or the partition id, and context id if real is false.
77     * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
78     * @param paritition_id partition this entry is for
79     * @param real is this a real->phys or virt->phys translation
80     * @param context_id if this is virt->phys what context
81     * @return A pointer to a tlb entry
82     */
83    TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0);
84
85    /** Insert a PTE into the TLB. */
86    void insert(Addr vpn, int partition_id, int context_id, bool real,
87            const PageTableEntry& PTE);
88
89    /** Given an entry id, read that tlb entries' tag. */
90    uint64_t TagRead(int entry);
91
92    /** Give an entry id, read that tlb entries' tte */
93    uint64_t TteRead(int entry);
94
95    /** Remove all entries from the TLB */
96    void invalidateAll();
97
98    /** Remove all non-locked entries from the tlb that match partition id. */
99    void demapAll(int partition_id);
100
101    /** Remove all entries that match a given context/partition id. */
102    void demapContext(int partition_id, int context_id);
103
104    /** Remve all entries that match a certain partition id, (contextid), and
105     * va). */
106    void demapPage(Addr va, int partition_id, bool real, int context_id);
107
108    /** Checks if the virtual address provided is a valid one. */
109    bool validVirtualAddress(Addr va, bool am);
110
111    void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
112            bool se, FaultTypes ft, int asi);
113
114    void TLB::clearUsedBits();
115
116
117  public:
118    TLB(const std::string &name, int size);
119
120    // Checkpointing
121    virtual void serialize(std::ostream &os);
122    virtual void unserialize(Checkpoint *cp, const std::string &section);
123};
124
125class ITB : public TLB
126{
127  public:
128    ITB(const std::string &name, int size) : TLB(name, size)
129    {
130    }
131
132    Fault translate(RequestPtr &req, ThreadContext *tc);
133  private:
134    void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
135            bool se, FaultTypes ft, int asi);
136};
137
138class DTB : public TLB
139{
140  public:
141    DTB(const std::string &name, int size) : TLB(name, size)
142    {
143    }
144
145    Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
146    Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
147    Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
148
149  private:
150    void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
151            bool se, FaultTypes ft, int asi);
152
153};
154
155}
156
157#endif // __ARCH_SPARC_TLB_HH__
158