tlb.hh revision 13913:16e9c0affcdd 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/generic/tlb.hh"
35#include "arch/sparc/asi.hh"
36#include "arch/sparc/tlb_map.hh"
37#include "base/logging.hh"
38#include "mem/request.hh"
39#include "params/SparcTLB.hh"
40
41class ThreadContext;
42class Packet;
43
44namespace SparcISA
45{
46
47const Addr StartVAddrHole = ULL(0x0000800000000000);
48const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
49const Addr VAddrAMask = ULL(0xFFFFFFFF);
50const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
51
52class TLB : public BaseTLB
53{
54    // These faults need to be able to populate the tlb in SE mode.
55    friend class FastInstructionAccessMMUMiss;
56    friend class FastDataAccessMMUMiss;
57
58    // TLB state
59  protected:
60    // Only used when this is the data TLB.
61    uint64_t sfar;
62    uint64_t c0_tsb_ps0;
63    uint64_t c0_tsb_ps1;
64    uint64_t c0_config;
65    uint64_t cx_tsb_ps0;
66    uint64_t cx_tsb_ps1;
67    uint64_t cx_config;
68    uint64_t sfsr;
69    uint64_t tag_access;
70
71  protected:
72    TlbMap lookupTable;;
73    typedef TlbMap::iterator MapIter;
74
75    TlbEntry *tlb;
76
77    int size;
78    int usedEntries;
79    int lastReplaced;
80
81    uint64_t cacheState;
82    bool cacheValid;
83
84    std::list<TlbEntry*> freeList;
85
86    enum FaultTypes {
87        OtherFault = 0,
88        PrivViolation = 0x1,
89        SideEffect = 0x2,
90        AtomicToIo = 0x4,
91        IllegalAsi = 0x8,
92        LoadFromNfo = 0x10,
93        VaOutOfRange = 0x20,
94        VaOutOfRangeJmp = 0x40
95    };
96
97    enum ContextType {
98        Primary = 0,
99        Secondary = 1,
100        Nucleus = 2
101    };
102
103    enum TsbPageSize {
104        Ps0,
105        Ps1
106    };
107  public:
108    /** lookup an entry in the TLB based on the partition id, and real bit if
109     * real is true or the partition id, and context id if real is false.
110     * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
111     * @param paritition_id partition this entry is for
112     * @param real is this a real->phys or virt->phys translation
113     * @param context_id if this is virt->phys what context
114     * @param update_used should ew update the used bits in the
115     * entries on not useful if we are trying to do a va->pa without
116     * mucking with any state for a debug read for example.
117     * @return A pointer to a tlb entry
118     */
119    TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
120            bool update_used = true);
121
122    /** Remove all entries from the TLB */
123    void flushAll() override;
124
125  protected:
126    /** Insert a PTE into the TLB. */
127    void insert(Addr vpn, int partition_id, int context_id, bool real,
128            const PageTableEntry& PTE, int entry = -1);
129
130    /** Given an entry id, read that tlb entries' tag. */
131    uint64_t TagRead(int entry);
132
133    /** Remove all non-locked entries from the tlb that match partition id. */
134    void demapAll(int partition_id);
135
136    /** Remove all entries that match a given context/partition id. */
137    void demapContext(int partition_id, int context_id);
138
139    /** Remve all entries that match a certain partition id, (contextid), and
140     * va). */
141    void demapPage(Addr va, int partition_id, bool real, int context_id);
142
143    /** Checks if the virtual address provided is a valid one. */
144    bool validVirtualAddress(Addr va, bool am);
145
146    void writeSfsr(bool write, ContextType ct,
147            bool se, FaultTypes ft, int asi);
148
149    void clearUsedBits();
150
151
152    void writeTagAccess(Addr va, int context);
153
154    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
155    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
156
157  public:
158    typedef SparcTLBParams Params;
159    TLB(const Params *p);
160
161    void takeOverFrom(BaseTLB *otlb) override {}
162
163    void
164    demapPage(Addr vaddr, uint64_t asn) override
165    {
166        panic("demapPage(Addr) is not implemented.\n");
167    }
168
169    void dumpAll();
170
171    Fault translateAtomic(
172            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
173    void translateTiming(
174            const RequestPtr &req, ThreadContext *tc,
175            Translation *translation, Mode mode) override;
176    Fault finalizePhysical(
177            const RequestPtr &req,
178            ThreadContext *tc, Mode mode) const override;
179    Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
180    Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
181    void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
182
183    // Checkpointing
184    void serialize(CheckpointOut &cp) const override;
185    void unserialize(CheckpointIn &cp) override;
186
187    /** Give an entry id, read that tlb entries' tte */
188    uint64_t TteRead(int entry);
189
190  private:
191    void writeSfsr(Addr a, bool write, ContextType ct,
192            bool se, FaultTypes ft, int asi);
193
194    uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
195        uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
196
197
198    TlbEntry *cacheEntry[2];
199    ASI cacheAsi[2];
200};
201
202}
203
204#endif // __ARCH_SPARC_TLB_HH__
205