tlb.hh revision 12749:223c83ed9979
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2006 The Regents of The University of Michigan 310037SARM gem5 Developers * All rights reserved. 410037SARM gem5 Developers * 510037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 610037SARM gem5 Developers * modification, are permitted provided that the following conditions are 710037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 810037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 910037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 1110037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 1210037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 1310037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 1410037SARM gem5 Developers * this software without specific prior written permission. 1510037SARM gem5 Developers * 1610037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710037SARM gem5 Developers * 2810037SARM gem5 Developers * Authors: Ali Saidi 2910037SARM gem5 Developers */ 3010037SARM gem5 Developers 3110037SARM gem5 Developers#ifndef __ARCH_SPARC_TLB_HH__ 3210037SARM gem5 Developers#define __ARCH_SPARC_TLB_HH__ 3310037SARM gem5 Developers 3410037SARM gem5 Developers#include "arch/generic/tlb.hh" 3510037SARM gem5 Developers#include "arch/sparc/asi.hh" 3610037SARM gem5 Developers#include "arch/sparc/tlb_map.hh" 3710037SARM gem5 Developers#include "base/logging.hh" 3810037SARM gem5 Developers#include "mem/request.hh" 3910037SARM gem5 Developers#include "params/SparcTLB.hh" 4010037SARM gem5 Developers 4110037SARM gem5 Developersclass ThreadContext; 4210037SARM gem5 Developersclass Packet; 4310037SARM gem5 Developers 4410037SARM gem5 Developersnamespace SparcISA 4510037SARM gem5 Developers{ 4610037SARM gem5 Developers 4710037SARM gem5 Developersclass TLB : public BaseTLB 4810037SARM gem5 Developers{ 4910037SARM gem5 Developers // These faults need to be able to populate the tlb in SE mode. 5010037SARM gem5 Developers friend class FastInstructionAccessMMUMiss; 5110037SARM gem5 Developers friend class FastDataAccessMMUMiss; 5210037SARM gem5 Developers 5310037SARM gem5 Developers // TLB state 5410037SARM gem5 Developers protected: 5510037SARM gem5 Developers // Only used when this is the data TLB. 5610037SARM gem5 Developers uint64_t sfar; 5710037SARM gem5 Developers uint64_t c0_tsb_ps0; 5810037SARM gem5 Developers uint64_t c0_tsb_ps1; 5910037SARM gem5 Developers uint64_t c0_config; 6010037SARM gem5 Developers uint64_t cx_tsb_ps0; 6110037SARM gem5 Developers uint64_t cx_tsb_ps1; 6210037SARM gem5 Developers uint64_t cx_config; 6310037SARM gem5 Developers uint64_t sfsr; 6410037SARM gem5 Developers uint64_t tag_access; 6510037SARM gem5 Developers 6610037SARM gem5 Developers protected: 6710037SARM gem5 Developers TlbMap lookupTable;; 6810037SARM gem5 Developers typedef TlbMap::iterator MapIter; 6910037SARM gem5 Developers 7010037SARM gem5 Developers TlbEntry *tlb; 7110037SARM gem5 Developers 7210037SARM gem5 Developers int size; 7310037SARM gem5 Developers int usedEntries; 7410037SARM gem5 Developers int lastReplaced; 7510037SARM gem5 Developers 7610037SARM gem5 Developers uint64_t cacheState; 7710037SARM gem5 Developers bool cacheValid; 7810037SARM gem5 Developers 7910037SARM gem5 Developers std::list<TlbEntry*> freeList; 8010037SARM gem5 Developers 8110037SARM gem5 Developers enum FaultTypes { 8210037SARM gem5 Developers OtherFault = 0, 8310037SARM gem5 Developers PrivViolation = 0x1, 8410037SARM gem5 Developers SideEffect = 0x2, 8510037SARM gem5 Developers AtomicToIo = 0x4, 8610037SARM gem5 Developers IllegalAsi = 0x8, 8710037SARM gem5 Developers LoadFromNfo = 0x10, 8810037SARM gem5 Developers VaOutOfRange = 0x20, 8910037SARM gem5 Developers VaOutOfRangeJmp = 0x40 9010037SARM gem5 Developers }; 9110037SARM gem5 Developers 9210037SARM gem5 Developers enum ContextType { 9310037SARM gem5 Developers Primary = 0, 9410037SARM gem5 Developers Secondary = 1, 9510037SARM gem5 Developers Nucleus = 2 9610037SARM gem5 Developers }; 9710037SARM gem5 Developers 9810037SARM gem5 Developers enum TsbPageSize { 9910037SARM gem5 Developers Ps0, 10010037SARM gem5 Developers Ps1 10110037SARM gem5 Developers }; 10210037SARM gem5 Developers public: 10310037SARM gem5 Developers /** lookup an entry in the TLB based on the partition id, and real bit if 10410037SARM gem5 Developers * real is true or the partition id, and context id if real is false. 10510037SARM gem5 Developers * @param va the virtual address not shifted (e.g. bottom 13 bits are 0) 10610037SARM gem5 Developers * @param paritition_id partition this entry is for 10710037SARM gem5 Developers * @param real is this a real->phys or virt->phys translation 10810037SARM gem5 Developers * @param context_id if this is virt->phys what context 10910037SARM gem5 Developers * @param update_used should ew update the used bits in the 11010037SARM gem5 Developers * entries on not useful if we are trying to do a va->pa without 11110037SARM gem5 Developers * mucking with any state for a debug read for example. 11210037SARM gem5 Developers * @return A pointer to a tlb entry 11310037SARM gem5 Developers */ 11410037SARM gem5 Developers TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0, 11510037SARM gem5 Developers bool update_used = true); 11610037SARM gem5 Developers 11710037SARM gem5 Developers /** Remove all entries from the TLB */ 11810037SARM gem5 Developers void flushAll() override; 11910037SARM gem5 Developers 12010037SARM gem5 Developers protected: 12110037SARM gem5 Developers /** Insert a PTE into the TLB. */ 12210037SARM gem5 Developers void insert(Addr vpn, int partition_id, int context_id, bool real, 12310037SARM gem5 Developers const PageTableEntry& PTE, int entry = -1); 12410037SARM gem5 Developers 12510037SARM gem5 Developers /** Given an entry id, read that tlb entries' tag. */ 12610037SARM gem5 Developers uint64_t TagRead(int entry); 12710037SARM gem5 Developers 12810037SARM gem5 Developers /** Remove all non-locked entries from the tlb that match partition id. */ 12910037SARM gem5 Developers void demapAll(int partition_id); 13010037SARM gem5 Developers 13110037SARM gem5 Developers /** Remove all entries that match a given context/partition id. */ 13210037SARM gem5 Developers void demapContext(int partition_id, int context_id); 13310037SARM gem5 Developers 13410037SARM gem5 Developers /** Remve all entries that match a certain partition id, (contextid), and 13510037SARM gem5 Developers * va). */ 13610037SARM gem5 Developers void demapPage(Addr va, int partition_id, bool real, int context_id); 13710037SARM gem5 Developers 13810037SARM gem5 Developers /** Checks if the virtual address provided is a valid one. */ 13910037SARM gem5 Developers bool validVirtualAddress(Addr va, bool am); 14010037SARM gem5 Developers 14110037SARM gem5 Developers void writeSfsr(bool write, ContextType ct, 14210037SARM gem5 Developers bool se, FaultTypes ft, int asi); 14310037SARM gem5 Developers 14410037SARM gem5 Developers void clearUsedBits(); 14510037SARM gem5 Developers 14610037SARM gem5 Developers 14710037SARM gem5 Developers void writeTagAccess(Addr va, int context); 14810037SARM gem5 Developers 14910037SARM gem5 Developers Fault translateInst(const RequestPtr &req, ThreadContext *tc); 15010037SARM gem5 Developers Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write); 15110037SARM gem5 Developers 15210037SARM gem5 Developers public: 15310037SARM gem5 Developers typedef SparcTLBParams Params; 15410037SARM gem5 Developers TLB(const Params *p); 15510037SARM gem5 Developers 15610037SARM gem5 Developers void takeOverFrom(BaseTLB *otlb) override {} 15710037SARM gem5 Developers 15810037SARM gem5 Developers void 15910037SARM gem5 Developers demapPage(Addr vaddr, uint64_t asn) override 16010037SARM gem5 Developers { 16110037SARM gem5 Developers panic("demapPage(Addr) is not implemented.\n"); 16210037SARM gem5 Developers } 16310037SARM gem5 Developers 16410037SARM gem5 Developers void dumpAll(); 16510037SARM gem5 Developers 16610037SARM gem5 Developers Fault translateAtomic( 16710037SARM gem5 Developers const RequestPtr &req, ThreadContext *tc, Mode mode) override; 16810037SARM gem5 Developers void translateTiming( 16910037SARM gem5 Developers const RequestPtr &req, ThreadContext *tc, 17010037SARM gem5 Developers Translation *translation, Mode mode) override; 17110037SARM gem5 Developers Fault finalizePhysical( 17210037SARM gem5 Developers const RequestPtr &req, 17310037SARM gem5 Developers ThreadContext *tc, Mode mode) const override; 17410037SARM gem5 Developers Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt); 17510037SARM gem5 Developers Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt); 17610037SARM gem5 Developers void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); 17710037SARM gem5 Developers 17810037SARM gem5 Developers // Checkpointing 17910037SARM gem5 Developers void serialize(CheckpointOut &cp) const override; 18010037SARM gem5 Developers void unserialize(CheckpointIn &cp) override; 18110037SARM gem5 Developers 18210037SARM gem5 Developers /** Give an entry id, read that tlb entries' tte */ 18310037SARM gem5 Developers uint64_t TteRead(int entry); 18410037SARM gem5 Developers 18510037SARM gem5 Developers private: 18610037SARM gem5 Developers void writeSfsr(Addr a, bool write, ContextType ct, 18710037SARM gem5 Developers bool se, FaultTypes ft, int asi); 18810037SARM gem5 Developers 18910037SARM gem5 Developers uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 19010037SARM gem5 Developers uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config); 19110037SARM gem5 Developers 19210037SARM gem5 Developers 19310037SARM gem5 Developers TlbEntry *cacheEntry[2]; 19410037SARM gem5 Developers ASI cacheAsi[2]; 19510037SARM gem5 Developers}; 19610037SARM gem5 Developers 19710037SARM gem5 Developers} 19810037SARM gem5 Developers 19910037SARM gem5 Developers#endif // __ARCH_SPARC_TLB_HH__ 20010037SARM gem5 Developers