process.cc revision 6335:a08470cb53e5
12SN/A/* 210905Sandreas.sandberg@arm.com * Copyright (c) 2003-2004 The Regents of The University of Michigan 310905Sandreas.sandberg@arm.com * All rights reserved. 410905Sandreas.sandberg@arm.com * 510905Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 610905Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 710905Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 810905Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 910905Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1010905Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1110905Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1210905Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1310905Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 159983Sstever@gmail.com * 169983Sstever@gmail.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Gabe Black 292SN/A * Ali Saidi 302SN/A */ 312SN/A 322SN/A#include "arch/sparc/asi.hh" 332SN/A#include "arch/sparc/handlers.hh" 342SN/A#include "arch/sparc/isa_traits.hh" 352SN/A#include "arch/sparc/registers.hh" 362SN/A#include "arch/sparc/process.hh" 372SN/A#include "arch/sparc/types.hh" 382SN/A#include "base/loader/object_file.hh" 392SN/A#include "base/loader/elf_object.hh" 402SN/A#include "base/misc.hh" 412665Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 422760Sbinkertn@umich.edu#include "mem/page_table.hh" 432760Sbinkertn@umich.edu#include "sim/process_impl.hh" 442665Ssaidi@eecs.umich.edu#include "mem/translating_port.hh" 4510905Sandreas.sandberg@arm.com#include "sim/system.hh" 462SN/A 472SN/Ausing namespace std; 488229Snate@binkert.orgusing namespace SparcISA; 492SN/A 50363SN/Astatic const int FirstArgumentReg = 8; 512SN/A 528229Snate@binkert.org 532SN/ASparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 542SN/A ObjectFile *objFile, Addr _StackBias) 552SN/A : LiveProcess(params, objFile), StackBias(_StackBias) 562SN/A{ 572SN/A 5810907Sandreas.sandberg@arm.com // XXX all the below need to be updated for SPARC - Ali 59363SN/A brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 6056SN/A brk_point = roundUp(brk_point, VMPageSize); 611388SN/A 62217SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 63363SN/A next_thread_stack_base = stack_base - (8 * 1024 * 1024); 6410905Sandreas.sandberg@arm.com 6556SN/A //Initialize these to 0s 6656SN/A fillStart = 0; 6756SN/A spillStart = 0; 681638SN/A} 6956SN/A 702SN/Avoid SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) 712356SN/A{ 722356SN/A switch(trapNum) 732356SN/A { 742SN/A case 0x01: //Software breakpoint 752SN/A warn("Software breakpoint encountered at pc %#x.\n", tc->readPC()); 764762Snate@binkert.org break; 774762Snate@binkert.org case 0x02: //Division by zero 784762Snate@binkert.org warn("Software signaled a division by zero at pc %#x.\n", 794762Snate@binkert.org tc->readPC()); 804762Snate@binkert.org break; 814762Snate@binkert.org case 0x03: //Flush window trap 824762Snate@binkert.org flushWindows(tc); 834762Snate@binkert.org break; 844762Snate@binkert.org case 0x04: //Clean windows 854762Snate@binkert.org warn("Ignoring process request for clean register " 864762Snate@binkert.org "windows at pc %#x.\n", tc->readPC()); 874762Snate@binkert.org break; 884762Snate@binkert.org case 0x05: //Range check 8910905Sandreas.sandberg@arm.com warn("Software signaled a range check at pc %#x.\n", 904762Snate@binkert.org tc->readPC()); 914762Snate@binkert.org break; 924762Snate@binkert.org case 0x06: //Fix alignment 934762Snate@binkert.org warn("Ignoring process request for os assisted unaligned accesses " 944762Snate@binkert.org "at pc %#x.\n", tc->readPC()); 954762Snate@binkert.org break; 964762Snate@binkert.org case 0x07: //Integer overflow 974762Snate@binkert.org warn("Software signaled an integer overflow at pc %#x.\n", 984762Snate@binkert.org tc->readPC()); 994762Snate@binkert.org break; 1004762Snate@binkert.org case 0x32: //Get integer condition codes 1014762Snate@binkert.org warn("Ignoring process request to get the integer condition codes " 1024762Snate@binkert.org "at pc %#x.\n", tc->readPC()); 1034762Snate@binkert.org break; 1044762Snate@binkert.org case 0x33: //Set integer condition codes 10510905Sandreas.sandberg@arm.com warn("Ignoring process request to set the integer condition codes " 1067494Ssteve.reinhardt@amd.com "at pc %#x.\n", tc->readPC()); 1077494Ssteve.reinhardt@amd.com break; 1087494Ssteve.reinhardt@amd.com default: 1097494Ssteve.reinhardt@amd.com panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 1107494Ssteve.reinhardt@amd.com } 1117494Ssteve.reinhardt@amd.com} 1127494Ssteve.reinhardt@amd.com 11310905Sandreas.sandberg@arm.comvoid 1144762Snate@binkert.orgSparcLiveProcess::startup() 1154762Snate@binkert.org{ 1164762Snate@binkert.org Process::startup(); 1174762Snate@binkert.org 1184762Snate@binkert.org ThreadContext *tc = system->getThreadContext(contextIds[0]); 1194762Snate@binkert.org //From the SPARC ABI 1204762Snate@binkert.org 12110905Sandreas.sandberg@arm.com //Setup default FP state 1224762Snate@binkert.org tc->setMiscRegNoEffect(MISCREG_FSR, 0); 1234762Snate@binkert.org 1244762Snate@binkert.org tc->setMiscRegNoEffect(MISCREG_TICK, 0); 1254762Snate@binkert.org 1264762Snate@binkert.org /* 1274762Snate@binkert.org * Register window management registers 1284762Snate@binkert.org */ 1294762Snate@binkert.org 1304762Snate@binkert.org //No windows contain info from other programs 13110386Sandreas.hansson@arm.com //tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 1324762Snate@binkert.org tc->setIntReg(NumIntArchRegs + 6, 0); 1334762Snate@binkert.org //There are no windows to pop 1344762Snate@binkert.org //tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 1354762Snate@binkert.org tc->setIntReg(NumIntArchRegs + 4, 0); 1364762Snate@binkert.org //All windows are available to save into 1374762Snate@binkert.org //tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 13810386Sandreas.hansson@arm.com tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 1394762Snate@binkert.org //All windows are "clean" 1404762Snate@binkert.org //tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 1414762Snate@binkert.org tc->setIntReg(NumIntArchRegs + 5, NWindows); 1424762Snate@binkert.org //Start with register window 0 1434762Snate@binkert.org tc->setMiscRegNoEffect(MISCREG_CWP, 0); 1444762Snate@binkert.org //Always use spill and fill traps 0 14510386Sandreas.hansson@arm.com //tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 1464762Snate@binkert.org tc->setIntReg(NumIntArchRegs + 7, 0); 1474762Snate@binkert.org //Set the trap level to 0 1484762Snate@binkert.org tc->setMiscRegNoEffect(MISCREG_TL, 0); 1494762Snate@binkert.org //Set the ASI register to something fixed 1504762Snate@binkert.org tc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); 15110905Sandreas.sandberg@arm.com 1524762Snate@binkert.org /* 1534762Snate@binkert.org * T1 specific registers 1544762Snate@binkert.org */ 1554762Snate@binkert.org //Turn on the icache, dcache, dtb translation, and itb translation. 1564762Snate@binkert.org tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 1574762Snate@binkert.org} 1584762Snate@binkert.org 1594762Snate@binkert.orgvoid 1604762Snate@binkert.orgSparc32LiveProcess::startup() 1614762Snate@binkert.org{ 1624762Snate@binkert.org if (checkpointRestored) 1634762Snate@binkert.org return; 1644762Snate@binkert.org 1654762Snate@binkert.org SparcLiveProcess::startup(); 1662287SN/A 1672287SN/A ThreadContext *tc = system->getThreadContext(contextIds[0]); 1682287SN/A //The process runs in user mode with 32 bit addresses 16910905Sandreas.sandberg@arm.com tc->setMiscReg(MISCREG_PSTATE, 0x0a); 1702SN/A 171217SN/A argsInit(32 / 8, VMPageSize); 1722SN/A} 17310905Sandreas.sandberg@arm.com 1742SN/Avoid 175217SN/ASparc64LiveProcess::startup() 176217SN/A{ 177217SN/A if (checkpointRestored) 1782SN/A return; 1792SN/A 1804841Ssaidi@eecs.umich.edu SparcLiveProcess::startup(); 1814841Ssaidi@eecs.umich.edu 18210905Sandreas.sandberg@arm.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 1834841Ssaidi@eecs.umich.edu //The process runs in user mode 1846227Snate@binkert.org tc->setMiscReg(MISCREG_PSTATE, 0x02); 1854841Ssaidi@eecs.umich.edu 1864841Ssaidi@eecs.umich.edu argsInit(sizeof(IntReg), VMPageSize); 1874841Ssaidi@eecs.umich.edu} 1886227Snate@binkert.org 1894841Ssaidi@eecs.umich.edutemplate<class IntType> 1904841Ssaidi@eecs.umich.eduvoid 1914841Ssaidi@eecs.umich.eduSparcLiveProcess::argsInit(int pageSize) 1924841Ssaidi@eecs.umich.edu{ 1934841Ssaidi@eecs.umich.edu int intSize = sizeof(IntType); 1944841Ssaidi@eecs.umich.edu 1957948SAli.Saidi@ARM.com typedef AuxVector<IntType> auxv_t; 1967948SAli.Saidi@ARM.com 19710905Sandreas.sandberg@arm.com std::vector<auxv_t> auxv; 1987948SAli.Saidi@ARM.com 1997948SAli.Saidi@ARM.com string filename; 2007948SAli.Saidi@ARM.com if(argv.size() < 1) 2017948SAli.Saidi@ARM.com filename = ""; 2027948SAli.Saidi@ARM.com else 2037948SAli.Saidi@ARM.com filename = argv[0]; 2047948SAli.Saidi@ARM.com 2057948SAli.Saidi@ARM.com //Even for a 32 bit process, the ABI says we still need to 2067948SAli.Saidi@ARM.com //maintain double word alignment of the stack pointer. 2077948SAli.Saidi@ARM.com uint64_t align = 16; 2087948SAli.Saidi@ARM.com 2097948SAli.Saidi@ARM.com // load object file into target memory 2107948SAli.Saidi@ARM.com objFile->loadSections(initVirtMem); 2117948SAli.Saidi@ARM.com 212217SN/A enum hardwareCaps 213217SN/A { 214217SN/A M5_HWCAP_SPARC_FLUSH = 1, 21510905Sandreas.sandberg@arm.com M5_HWCAP_SPARC_STBAR = 2, 2162SN/A M5_HWCAP_SPARC_SWAP = 4, 21710905Sandreas.sandberg@arm.com M5_HWCAP_SPARC_MULDIV = 8, 2186225Snate@binkert.org M5_HWCAP_SPARC_V9 = 16, 21910905Sandreas.sandberg@arm.com //This one should technically only be set 220217SN/A //if there is a cheetah or cheetah_plus tlb, 221217SN/A //but we'll use it all the time 2222SN/A M5_HWCAP_SPARC_ULTRA3 = 32 2232SN/A }; 2246820SLisa.Hsu@amd.com 2256820SLisa.Hsu@amd.com const int64_t hwcap = 22610905Sandreas.sandberg@arm.com M5_HWCAP_SPARC_FLUSH | 2276820SLisa.Hsu@amd.com M5_HWCAP_SPARC_STBAR | 22810905Sandreas.sandberg@arm.com M5_HWCAP_SPARC_SWAP | 2296820SLisa.Hsu@amd.com M5_HWCAP_SPARC_MULDIV | 23010905Sandreas.sandberg@arm.com M5_HWCAP_SPARC_V9 | 2316820SLisa.Hsu@amd.com M5_HWCAP_SPARC_ULTRA3; 2326820SLisa.Hsu@amd.com 2336820SLisa.Hsu@amd.com //Setup the auxilliary vectors. These will already have endian conversion. 2346820SLisa.Hsu@amd.com //Auxilliary vectors are loaded only for elf formatted executables. 2356820SLisa.Hsu@amd.com ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 2366820SLisa.Hsu@amd.com if(elfObject) 237217SN/A { 238217SN/A //Bits which describe the system hardware capabilities 239217SN/A auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 24010905Sandreas.sandberg@arm.com //The system page size 24110905Sandreas.sandberg@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize)); 242217SN/A //Defined to be 100 in the kernel source. 243217SN/A //Frequency at which times() increments 244217SN/A auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 245217SN/A // For statically linked executables, this is the virtual address of the 2466227Snate@binkert.org // program header tables if they appear in the executable image 247217SN/A auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 248217SN/A // This is the size of a program header entry from the elf file. 249217SN/A auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 250217SN/A // This is the number of program headers from the original elf file. 251217SN/A auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 252217SN/A //This is the address of the elf "interpreter", It should be set 253217SN/A //to 0 for regular executables. It should be something else 254217SN/A //(not sure what) for dynamic libraries. 255217SN/A auxv.push_back(auxv_t(M5_AT_BASE, 0)); 25610905Sandreas.sandberg@arm.com //This is hardwired to 0 in the elf loading code in the kernel 257217SN/A auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 25810905Sandreas.sandberg@arm.com //The entry point to the program 2596225Snate@binkert.org auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 26010905Sandreas.sandberg@arm.com //Different user and group IDs 261217SN/A auxv.push_back(auxv_t(M5_AT_UID, uid())); 262217SN/A auxv.push_back(auxv_t(M5_AT_EUID, euid())); 263217SN/A auxv.push_back(auxv_t(M5_AT_GID, gid())); 264217SN/A auxv.push_back(auxv_t(M5_AT_EGID, egid())); 265217SN/A //Whether to enable "secure mode" in the executable 266217SN/A auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 267217SN/A } 268217SN/A 269217SN/A //Figure out how big the initial stack needs to be 270217SN/A 271217SN/A // The unaccounted for 8 byte 0 at the top of the stack 272217SN/A int sentry_size = 8; 273217SN/A 274217SN/A //This is the name of the file which is present on the initial stack 275217SN/A //It's purpose is to let the user space linker examine the original file. 276217SN/A int file_name_size = filename.size() + 1; 277217SN/A 2786227Snate@binkert.org int env_data_size = 0; 279217SN/A for (int i = 0; i < envp.size(); ++i) { 280217SN/A env_data_size += envp[i].size() + 1; 281217SN/A } 282217SN/A int arg_data_size = 0; 28310905Sandreas.sandberg@arm.com for (int i = 0; i < argv.size(); ++i) { 284217SN/A arg_data_size += argv[i].size() + 1; 285217SN/A } 286217SN/A 287217SN/A //The info_block. 288217SN/A int base_info_block_size = 289217SN/A sentry_size + file_name_size + env_data_size + arg_data_size; 290217SN/A 291217SN/A int info_block_size = roundUp(base_info_block_size, align); 292217SN/A 293217SN/A int info_block_padding = info_block_size - base_info_block_size; 294217SN/A 295217SN/A //Each auxilliary vector is two words 296217SN/A int aux_array_size = intSize * 2 * (auxv.size() + 1); 297217SN/A 2984841Ssaidi@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 2994841Ssaidi@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 30010905Sandreas.sandberg@arm.com 3014841Ssaidi@eecs.umich.edu int argc_size = intSize; 30210905Sandreas.sandberg@arm.com int window_save_size = intSize * 16; 3036225Snate@binkert.org 30410905Sandreas.sandberg@arm.com //Figure out the size of the contents of the actual initial frame 3054841Ssaidi@eecs.umich.edu int frame_size = 3064841Ssaidi@eecs.umich.edu aux_array_size + 3074841Ssaidi@eecs.umich.edu envp_array_size + 3084841Ssaidi@eecs.umich.edu argv_array_size + 3094841Ssaidi@eecs.umich.edu argc_size + 3104841Ssaidi@eecs.umich.edu window_save_size; 3114841Ssaidi@eecs.umich.edu 3124841Ssaidi@eecs.umich.edu //There needs to be padding after the auxiliary vector data so that the 3134841Ssaidi@eecs.umich.edu //very bottom of the stack is aligned properly. 3144841Ssaidi@eecs.umich.edu int aligned_partial_size = roundUp(frame_size, align); 3154841Ssaidi@eecs.umich.edu int aux_padding = aligned_partial_size - frame_size; 3164841Ssaidi@eecs.umich.edu 3174841Ssaidi@eecs.umich.edu int space_needed = 3184841Ssaidi@eecs.umich.edu info_block_size + 3194841Ssaidi@eecs.umich.edu aux_padding + 3206227Snate@binkert.org frame_size; 3214841Ssaidi@eecs.umich.edu 3224841Ssaidi@eecs.umich.edu stack_min = stack_base - space_needed; 3234841Ssaidi@eecs.umich.edu stack_min = roundDown(stack_min, align); 3244841Ssaidi@eecs.umich.edu stack_size = stack_base - stack_min; 32510905Sandreas.sandberg@arm.com 3264841Ssaidi@eecs.umich.edu // Allocate space for the stack 3274841Ssaidi@eecs.umich.edu pTable->allocate(roundDown(stack_min, pageSize), 3284841Ssaidi@eecs.umich.edu roundUp(stack_size, pageSize)); 3294841Ssaidi@eecs.umich.edu 3304841Ssaidi@eecs.umich.edu // map out initial stack contents 3314841Ssaidi@eecs.umich.edu IntType sentry_base = stack_base - sentry_size; 3324841Ssaidi@eecs.umich.edu IntType file_name_base = sentry_base - file_name_size; 3334841Ssaidi@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 3344841Ssaidi@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 3354841Ssaidi@eecs.umich.edu IntType auxv_array_base = arg_data_base - 3364841Ssaidi@eecs.umich.edu info_block_padding - aux_array_size - aux_padding; 3374841Ssaidi@eecs.umich.edu IntType envp_array_base = auxv_array_base - envp_array_size; 3384841Ssaidi@eecs.umich.edu IntType argv_array_base = envp_array_base - argv_array_size; 3394841Ssaidi@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 3407948SAli.Saidi@ARM.com#if TRACING_ON 3417948SAli.Saidi@ARM.com IntType window_save_base = argc_base - window_save_size; 34210905Sandreas.sandberg@arm.com#endif 3437948SAli.Saidi@ARM.com 34410905Sandreas.sandberg@arm.com DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 3457948SAli.Saidi@ARM.com DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 34610905Sandreas.sandberg@arm.com DPRINTF(Stack, "filename = %s\n", filename); 3477948SAli.Saidi@ARM.com DPRINTF(Stack, "%#x - file name\n", file_name_base); 3487948SAli.Saidi@ARM.com DPRINTF(Stack, "%#x - env data\n", env_data_base); 3497948SAli.Saidi@ARM.com DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 3507948SAli.Saidi@ARM.com DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 3517948SAli.Saidi@ARM.com DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 3527948SAli.Saidi@ARM.com DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 3537948SAli.Saidi@ARM.com DPRINTF(Stack, "%#x - argc \n", argc_base); 3547948SAli.Saidi@ARM.com DPRINTF(Stack, "%#x - window save\n", window_save_base); 35510905Sandreas.sandberg@arm.com DPRINTF(Stack, "%#x - stack min\n", stack_min); 3567948SAli.Saidi@ARM.com 3577948SAli.Saidi@ARM.com assert(window_save_base == stack_min); 3587948SAli.Saidi@ARM.com 3597948SAli.Saidi@ARM.com // write contents to stack 3607948SAli.Saidi@ARM.com 3617948SAli.Saidi@ARM.com // figure out argc 3627948SAli.Saidi@ARM.com IntType argc = argv.size(); 3637948SAli.Saidi@ARM.com IntType guestArgc = SparcISA::htog(argc); 3647948SAli.Saidi@ARM.com 3657948SAli.Saidi@ARM.com //Write out the sentry void * 3667948SAli.Saidi@ARM.com uint64_t sentry_NULL = 0; 3677948SAli.Saidi@ARM.com initVirtMem->writeBlob(sentry_base, 3687948SAli.Saidi@ARM.com (uint8_t*)&sentry_NULL, sentry_size); 3697948SAli.Saidi@ARM.com 3707948SAli.Saidi@ARM.com //Write the file name 371237SN/A initVirtMem->writeString(file_name_base, filename.c_str()); 37210905Sandreas.sandberg@arm.com 373237SN/A //Copy the aux stuff 37410905Sandreas.sandberg@arm.com for(int x = 0; x < auxv.size(); x++) 37510905Sandreas.sandberg@arm.com { 376237SN/A initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, 377237SN/A (uint8_t*)&(auxv[x].a_type), intSize); 378237SN/A initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 379237SN/A (uint8_t*)&(auxv[x].a_val), intSize); 380237SN/A } 3815543Ssaidi@eecs.umich.edu 38210905Sandreas.sandberg@arm.com //Write out the terminating zeroed auxilliary vector 38310905Sandreas.sandberg@arm.com const IntType zero = 0; 38410905Sandreas.sandberg@arm.com initVirtMem->writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 38510905Sandreas.sandberg@arm.com (uint8_t*)&zero, intSize); 38610905Sandreas.sandberg@arm.com initVirtMem->writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 38710905Sandreas.sandberg@arm.com (uint8_t*)&zero, intSize); 38810905Sandreas.sandberg@arm.com 38910905Sandreas.sandberg@arm.com copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 39010905Sandreas.sandberg@arm.com copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 39110905Sandreas.sandberg@arm.com 39210905Sandreas.sandberg@arm.com initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 39310905Sandreas.sandberg@arm.com 39410905Sandreas.sandberg@arm.com //Set up space for the trap handlers into the processes address space. 39510905Sandreas.sandberg@arm.com //Since the stack grows down and there is reserved address space abov 39610905Sandreas.sandberg@arm.com //it, we can put stuff above it and stay out of the way. 39710905Sandreas.sandberg@arm.com fillStart = stack_base; 39810905Sandreas.sandberg@arm.com spillStart = fillStart + sizeof(MachInst) * numFillInsts; 39910905Sandreas.sandberg@arm.com 40010905Sandreas.sandberg@arm.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 40110905Sandreas.sandberg@arm.com //Set up the thread context to start running the process 40210905Sandreas.sandberg@arm.com //assert(NumArgumentRegs >= 2); 40310905Sandreas.sandberg@arm.com //tc->setIntReg(ArgumentReg[0], argc); 40410905Sandreas.sandberg@arm.com //tc->setIntReg(ArgumentReg[1], argv_array_base); 40510905Sandreas.sandberg@arm.com tc->setIntReg(StackPointerReg, stack_min - StackBias); 406217SN/A 4077494Ssteve.reinhardt@amd.com // %g1 is a pointer to a function that should be run at exit. Since we 4081642SN/A // don't have anything like that, it should be set to 0. 4091642SN/A tc->setIntReg(1, 0); 4101642SN/A 4111642SN/A Addr prog_entry = objFile->entryPoint(); 4121642SN/A tc->setPC(prog_entry); 4131642SN/A tc->setNextPC(prog_entry + sizeof(MachInst)); 4141642SN/A tc->setNextNPC(prog_entry + (2 * sizeof(MachInst))); 4151642SN/A 4161642SN/A //Align the "stack_min" to a page boundary. 4171642SN/A stack_min = roundDown(stack_min, pageSize); 418219SN/A 4195992Snate@binkert.org// num_processes++; 4205992Snate@binkert.org} 421217SN/A 42210907Sandreas.sandberg@arm.comvoid 423217SN/ASparc64LiveProcess::argsInit(int intSize, int pageSize) 424217SN/A{ 425395SN/A SparcLiveProcess::argsInit<uint64_t>(pageSize); 426395SN/A 427395SN/A // Stuff the trap handlers into the process address space 428395SN/A initVirtMem->writeBlob(fillStart, 429395SN/A (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 4302SN/A initVirtMem->writeBlob(spillStart, 431395SN/A (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 43210905Sandreas.sandberg@arm.com} 43310905Sandreas.sandberg@arm.com 43410905Sandreas.sandberg@arm.comvoid 43510905Sandreas.sandberg@arm.comSparc32LiveProcess::argsInit(int intSize, int pageSize) 43610905Sandreas.sandberg@arm.com{ 43710905Sandreas.sandberg@arm.com SparcLiveProcess::argsInit<uint32_t>(pageSize); 43810905Sandreas.sandberg@arm.com 439395SN/A // Stuff the trap handlers into the process address space 4402SN/A initVirtMem->writeBlob(fillStart, 441395SN/A (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 442395SN/A initVirtMem->writeBlob(spillStart, 4432SN/A (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 44410905Sandreas.sandberg@arm.com} 44510905Sandreas.sandberg@arm.com 4462SN/Avoid Sparc32LiveProcess::flushWindows(ThreadContext *tc) 44710905Sandreas.sandberg@arm.com{ 4482SN/A IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4492SN/A IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4502SN/A IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 45110905Sandreas.sandberg@arm.com MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4522SN/A MiscReg origCWP = CWP; 45310905Sandreas.sandberg@arm.com CWP = (CWP + Cansave + 2) % NWindows; 4542SN/A while(NWindows - 2 - Cansave != 0) 4552SN/A { 4565739Snate@binkert.org if (Otherwin) { 4575739Snate@binkert.org panic("Otherwin non-zero.\n"); 4585739Snate@binkert.org } else { 4595739Snate@binkert.org tc->setMiscReg(MISCREG_CWP, CWP); 4605739Snate@binkert.org //Do the stores 4615739Snate@binkert.org IntReg sp = tc->readIntReg(StackPointerReg); 4625739Snate@binkert.org for (int index = 16; index < 32; index++) { 4635739Snate@binkert.org uint32_t regVal = tc->readIntReg(index); 4645739Snate@binkert.org regVal = htog(regVal); 46510905Sandreas.sandberg@arm.com if (!tc->getMemPort()->tryWriteBlob( 4665739Snate@binkert.org sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 46710905Sandreas.sandberg@arm.com warn("Failed to save register to the stack when " 46810905Sandreas.sandberg@arm.com "flushing windows.\n"); 4695739Snate@binkert.org } 4705739Snate@binkert.org } 4715739Snate@binkert.org Canrestore--; 47210905Sandreas.sandberg@arm.com Cansave++; 4735739Snate@binkert.org CWP = (CWP + 1) % NWindows; 47410905Sandreas.sandberg@arm.com } 47510905Sandreas.sandberg@arm.com } 47610905Sandreas.sandberg@arm.com tc->setIntReg(NumIntArchRegs + 3, Cansave); 47710905Sandreas.sandberg@arm.com tc->setIntReg(NumIntArchRegs + 4, Canrestore); 47810905Sandreas.sandberg@arm.com tc->setMiscReg(MISCREG_CWP, origCWP); 47910905Sandreas.sandberg@arm.com} 48010905Sandreas.sandberg@arm.com 48110905Sandreas.sandberg@arm.comvoid Sparc64LiveProcess::flushWindows(ThreadContext *tc) 48210905Sandreas.sandberg@arm.com{ 4835739Snate@binkert.org IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4845739Snate@binkert.org IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4852SN/A IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4866225Snate@binkert.org MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4872SN/A MiscReg origCWP = CWP; 48810905Sandreas.sandberg@arm.com CWP = (CWP + Cansave + 2) % NWindows; 489363SN/A while(NWindows - 2 - Cansave != 0) 490449SN/A { 491363SN/A if (Otherwin) { 49210905Sandreas.sandberg@arm.com panic("Otherwin non-zero.\n"); 493395SN/A } else { 4942SN/A tc->setMiscReg(MISCREG_CWP, CWP); 4955581Ssaidi@eecs.umich.edu //Do the stores 4965581Ssaidi@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4976818SLisa.Hsu@amd.com for (int index = 16; index < 32; index++) { 4982SN/A IntReg regVal = tc->readIntReg(index); 49910905Sandreas.sandberg@arm.com regVal = htog(regVal); 50010905Sandreas.sandberg@arm.com if (!tc->getMemPort()->tryWriteBlob( 501395SN/A sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 502395SN/A warn("Failed to save register to the stack when " 5032SN/A "flushing windows.\n"); 5042797Sktlim@umich.edu } 50510905Sandreas.sandberg@arm.com } 506395SN/A Canrestore--; 50710905Sandreas.sandberg@arm.com Cansave++; 50810905Sandreas.sandberg@arm.com CWP = (CWP + 1) % NWindows; 50911072Sandreas.sandberg@arm.com } 51010905Sandreas.sandberg@arm.com } 51110905Sandreas.sandberg@arm.com tc->setIntReg(NumIntArchRegs + 3, Cansave); 51210905Sandreas.sandberg@arm.com tc->setIntReg(NumIntArchRegs + 4, Canrestore); 51310905Sandreas.sandberg@arm.com tc->setMiscReg(MISCREG_CWP, origCWP); 51410905Sandreas.sandberg@arm.com} 51510905Sandreas.sandberg@arm.com 51610905Sandreas.sandberg@arm.comIntReg 51710905Sandreas.sandberg@arm.comSparc32LiveProcess::getSyscallArg(ThreadContext *tc, int i) 51810905Sandreas.sandberg@arm.com{ 51910905Sandreas.sandberg@arm.com assert(i < 6); 52010905Sandreas.sandberg@arm.com return bits(tc->readIntReg(FirstArgumentReg + i), 31, 0); 52110905Sandreas.sandberg@arm.com} 52210905Sandreas.sandberg@arm.com 52310905Sandreas.sandberg@arm.comvoid 52410905Sandreas.sandberg@arm.comSparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 52510905Sandreas.sandberg@arm.com{ 52610905Sandreas.sandberg@arm.com assert(i < 6); 52710905Sandreas.sandberg@arm.com tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 52810905Sandreas.sandberg@arm.com} 52910905Sandreas.sandberg@arm.com 53010905Sandreas.sandberg@arm.comIntReg 53110905Sandreas.sandberg@arm.comSparc64LiveProcess::getSyscallArg(ThreadContext *tc, int i) 53210905Sandreas.sandberg@arm.com{ 53310905Sandreas.sandberg@arm.com assert(i < 6); 53410905Sandreas.sandberg@arm.com return tc->readIntReg(FirstArgumentReg + i); 53510905Sandreas.sandberg@arm.com} 53610905Sandreas.sandberg@arm.com 537395SN/Avoid 5382SN/ASparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5392SN/A{ 5406225Snate@binkert.org assert(i < 6); 5412SN/A tc->setIntReg(FirstArgumentReg + i, val); 5422868Sktlim@umich.edu} 5432SN/A 5442SN/Avoid 54510905Sandreas.sandberg@arm.comSparcLiveProcess::setSyscallReturn(ThreadContext *tc, 54610905Sandreas.sandberg@arm.com SyscallReturn return_value) 54710905Sandreas.sandberg@arm.com{ 54810905Sandreas.sandberg@arm.com // check for error condition. SPARC syscall convention is to 54910905Sandreas.sandberg@arm.com // indicate success/failure in reg the carry bit of the ccr 55010905Sandreas.sandberg@arm.com // and put the return value itself in the standard return value reg (). 55110905Sandreas.sandberg@arm.com if (return_value.successful()) { 552237SN/A // no error, clear XCC.C 55310905Sandreas.sandberg@arm.com tc->setIntReg(NumIntArchRegs + 2, 5547491Ssteve.reinhardt@amd.com tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 55510905Sandreas.sandberg@arm.com //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE); 5567491Ssteve.reinhardt@amd.com IntReg val = return_value.value(); 5577491Ssteve.reinhardt@amd.com if (bits(tc->readMiscRegNoEffect( 55810905Sandreas.sandberg@arm.com SparcISA::MISCREG_PSTATE), 3, 3)) { 5597491Ssteve.reinhardt@amd.com val = bits(val, 31, 0); 5607823Ssteve.reinhardt@amd.com } 5617491Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, val); 5627491Ssteve.reinhardt@amd.com } else { 5637823Ssteve.reinhardt@amd.com // got an error, set XCC.C 5647491Ssteve.reinhardt@amd.com tc->setIntReg(NumIntArchRegs + 2, 5657491Ssteve.reinhardt@amd.com tc->readIntReg(NumIntArchRegs + 2) | 0x11); 5667491Ssteve.reinhardt@amd.com //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11); 5677491Ssteve.reinhardt@amd.com IntReg val = -return_value.value(); 5687491Ssteve.reinhardt@amd.com if (bits(tc->readMiscRegNoEffect( 5697491Ssteve.reinhardt@amd.com SparcISA::MISCREG_PSTATE), 3, 3)) { 57010905Sandreas.sandberg@arm.com val = bits(val, 31, 0); 5717491Ssteve.reinhardt@amd.com } 5727491Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, val); 5737491Ssteve.reinhardt@amd.com } 5747491Ssteve.reinhardt@amd.com} 5757491Ssteve.reinhardt@amd.com