process.cc revision 5713:993c7952b930
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2003-2004 The Regents of The University of Michigan 37414SAli.Saidi@ARM.com * All rights reserved. 47414SAli.Saidi@ARM.com * 57414SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67414SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77414SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87414SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97414SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107414SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117414SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127414SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137414SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Gabe Black 296019Shines@cs.fsu.edu * Ali Saidi 306019Shines@cs.fsu.edu */ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu#include "arch/sparc/asi.hh" 336019Shines@cs.fsu.edu#include "arch/sparc/handlers.hh" 346019Shines@cs.fsu.edu#include "arch/sparc/isa_traits.hh" 356019Shines@cs.fsu.edu#include "arch/sparc/process.hh" 366019Shines@cs.fsu.edu#include "arch/sparc/types.hh" 376019Shines@cs.fsu.edu#include "base/loader/object_file.hh" 386019Shines@cs.fsu.edu#include "base/loader/elf_object.hh" 396019Shines@cs.fsu.edu#include "base/misc.hh" 406019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 417414SAli.Saidi@ARM.com#include "mem/page_table.hh" 426019Shines@cs.fsu.edu#include "sim/process_impl.hh" 436019Shines@cs.fsu.edu#include "mem/translating_port.hh" 4411793Sbrandon.potter@amd.com#include "sim/system.hh" 4511793Sbrandon.potter@amd.com 466019Shines@cs.fsu.eduusing namespace std; 476019Shines@cs.fsu.eduusing namespace SparcISA; 486019Shines@cs.fsu.edu 496019Shines@cs.fsu.edu 506019Shines@cs.fsu.eduSparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 516019Shines@cs.fsu.edu ObjectFile *objFile, Addr _StackBias) 528232Snate@binkert.org : LiveProcess(params, objFile), StackBias(_StackBias) 536019Shines@cs.fsu.edu{ 5411854Sbrandon.potter@amd.com 557678Sgblack@eecs.umich.edu // XXX all the below need to be updated for SPARC - Ali 566019Shines@cs.fsu.edu brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 5711800Sbrandon.potter@amd.com brk_point = roundUp(brk_point, VMPageSize); 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edu // Set pointer for next thread stack. Reserve 8M for main stack. 606019Shines@cs.fsu.edu next_thread_stack_base = stack_base - (8 * 1024 * 1024); 616019Shines@cs.fsu.edu 626019Shines@cs.fsu.edu //Initialize these to 0s 6311851Sbrandon.potter@amd.com fillStart = 0; 6411851Sbrandon.potter@amd.com spillStart = 0; 6511851Sbrandon.potter@amd.com} 666019Shines@cs.fsu.edu 6710037SARM gem5 Developersvoid SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) 6810037SARM gem5 Developers{ 6911851Sbrandon.potter@amd.com switch(trapNum) 7011851Sbrandon.potter@amd.com { 7111851Sbrandon.potter@amd.com case 0x01: //Software breakpoint 7210037SARM gem5 Developers warn("Software breakpoint encountered at pc %#x.\n", tc->readPC()); 7311886Sbrandon.potter@amd.com break; 746019Shines@cs.fsu.edu case 0x02: //Division by zero 756019Shines@cs.fsu.edu warn("Software signaled a division by zero at pc %#x.\n", 7611886Sbrandon.potter@amd.com tc->readPC()); 776019Shines@cs.fsu.edu break; 786019Shines@cs.fsu.edu case 0x03: //Flush window trap 7911886Sbrandon.potter@amd.com flushWindows(tc); 8011886Sbrandon.potter@amd.com break; 8111886Sbrandon.potter@amd.com case 0x04: //Clean windows 826019Shines@cs.fsu.edu warn("Ignoring process request for clean register " 836019Shines@cs.fsu.edu "windows at pc %#x.\n", tc->readPC()); 8411886Sbrandon.potter@amd.com break; 856019Shines@cs.fsu.edu case 0x05: //Range check 866019Shines@cs.fsu.edu warn("Software signaled a range check at pc %#x.\n", 8711851Sbrandon.potter@amd.com tc->readPC()); 8811851Sbrandon.potter@amd.com break; 8911851Sbrandon.potter@amd.com case 0x06: //Fix alignment 9010037SARM gem5 Developers warn("Ignoring process request for os assisted unaligned accesses " 9111886Sbrandon.potter@amd.com "at pc %#x.\n", tc->readPC()); 9210037SARM gem5 Developers break; 9310037SARM gem5 Developers case 0x07: //Integer overflow 9411886Sbrandon.potter@amd.com warn("Software signaled an integer overflow at pc %#x.\n", 9510037SARM gem5 Developers tc->readPC()); 9610037SARM gem5 Developers break; 9711886Sbrandon.potter@amd.com case 0x32: //Get integer condition codes 9811886Sbrandon.potter@amd.com warn("Ignoring process request to get the integer condition codes " 9911886Sbrandon.potter@amd.com "at pc %#x.\n", tc->readPC()); 10010037SARM gem5 Developers break; 10110037SARM gem5 Developers case 0x33: //Set integer condition codes 10211886Sbrandon.potter@amd.com warn("Ignoring process request to set the integer condition codes " 10310037SARM gem5 Developers "at pc %#x.\n", tc->readPC()); 10410037SARM gem5 Developers break; 1056019Shines@cs.fsu.edu default: 10611851Sbrandon.potter@amd.com panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 1076019Shines@cs.fsu.edu } 10811851Sbrandon.potter@amd.com} 10910318Sandreas.hansson@arm.com 1107640Sgblack@eecs.umich.eduvoid 1117640Sgblack@eecs.umich.eduSparcLiveProcess::startup() 1127640Sgblack@eecs.umich.edu{ 1137640Sgblack@eecs.umich.edu Process::startup(); 1147640Sgblack@eecs.umich.edu 1157640Sgblack@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1167640Sgblack@eecs.umich.edu //From the SPARC ABI 1177640Sgblack@eecs.umich.edu 1187640Sgblack@eecs.umich.edu //Setup default FP state 1197640Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_FSR, 0); 1207640Sgblack@eecs.umich.edu 1217640Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TICK, 0); 1226019Shines@cs.fsu.edu 1236019Shines@cs.fsu.edu /* 1246019Shines@cs.fsu.edu * Register window management registers 12511851Sbrandon.potter@amd.com */ 1266019Shines@cs.fsu.edu 12711851Sbrandon.potter@amd.com //No windows contain info from other programs 12810318Sandreas.hansson@arm.com //tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 12910037SARM gem5 Developers tc->setIntReg(NumIntArchRegs + 6, 0); 13010037SARM gem5 Developers //There are no windows to pop 13110037SARM gem5 Developers //tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 13210037SARM gem5 Developers tc->setIntReg(NumIntArchRegs + 4, 0); 13310037SARM gem5 Developers //All windows are available to save into 13410037SARM gem5 Developers //tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 13510037SARM gem5 Developers tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 13610037SARM gem5 Developers //All windows are "clean" 13710037SARM gem5 Developers //tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 13810037SARM gem5 Developers tc->setIntReg(NumIntArchRegs + 5, NWindows); 13910037SARM gem5 Developers //Start with register window 0 14010037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_CWP, 0); 14110037SARM gem5 Developers //Always use spill and fill traps 0 14210037SARM gem5 Developers //tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 14310037SARM gem5 Developers tc->setIntReg(NumIntArchRegs + 7, 0); 14410037SARM gem5 Developers //Set the trap level to 0 14510037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_TL, 0); 14610037SARM gem5 Developers //Set the ASI register to something fixed 14710037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); 14811851Sbrandon.potter@amd.com 14910037SARM gem5 Developers /* 15010037SARM gem5 Developers * T1 specific registers 15110037SARM gem5 Developers */ 15210037SARM gem5 Developers //Turn on the icache, dcache, dtb translation, and itb translation. 1536400Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 1546400Sgblack@eecs.umich.edu} 1556400Sgblack@eecs.umich.edu 1566400Sgblack@eecs.umich.eduvoid 1576400Sgblack@eecs.umich.eduSparc32LiveProcess::startup() 1586400Sgblack@eecs.umich.edu{ 1596400Sgblack@eecs.umich.edu if (checkpointRestored) 1606400Sgblack@eecs.umich.edu return; 1616400Sgblack@eecs.umich.edu 1626400Sgblack@eecs.umich.edu SparcLiveProcess::startup(); 1636400Sgblack@eecs.umich.edu 16411389Sbrandon.potter@amd.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 16511389Sbrandon.potter@amd.com //The process runs in user mode with 32 bit addresses 16611389Sbrandon.potter@amd.com tc->setMiscReg(MISCREG_PSTATE, 0x0a); 1676019Shines@cs.fsu.edu 1686019Shines@cs.fsu.edu argsInit(32 / 8, VMPageSize); 1696019Shines@cs.fsu.edu} 1706400Sgblack@eecs.umich.edu 1716400Sgblack@eecs.umich.eduvoid 1726400Sgblack@eecs.umich.eduSparc64LiveProcess::startup() 1736400Sgblack@eecs.umich.edu{ 1746400Sgblack@eecs.umich.edu if (checkpointRestored) 1756400Sgblack@eecs.umich.edu return; 1766400Sgblack@eecs.umich.edu 1776400Sgblack@eecs.umich.edu SparcLiveProcess::startup(); 1786400Sgblack@eecs.umich.edu 1796400Sgblack@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1806400Sgblack@eecs.umich.edu //The process runs in user mode 1817414SAli.Saidi@ARM.com tc->setMiscReg(MISCREG_PSTATE, 0x02); 1827414SAli.Saidi@ARM.com 1837414SAli.Saidi@ARM.com argsInit(sizeof(IntReg), VMPageSize); 1847414SAli.Saidi@ARM.com} 1857414SAli.Saidi@ARM.com 1866400Sgblack@eecs.umich.edutemplate<class IntType> 1876400Sgblack@eecs.umich.eduvoid 1886400Sgblack@eecs.umich.eduSparcLiveProcess::argsInit(int pageSize) 1896400Sgblack@eecs.umich.edu{ 1906400Sgblack@eecs.umich.edu int intSize = sizeof(IntType); 1916400Sgblack@eecs.umich.edu 1926400Sgblack@eecs.umich.edu typedef M5_auxv_t<IntType> auxv_t; 19310810Sbr@bsdpad.com 19410810Sbr@bsdpad.com std::vector<auxv_t> auxv; 19510810Sbr@bsdpad.com 19610810Sbr@bsdpad.com string filename; 19710810Sbr@bsdpad.com if(argv.size() < 1) 19810810Sbr@bsdpad.com filename = ""; 19910810Sbr@bsdpad.com else 20010810Sbr@bsdpad.com filename = argv[0]; 20110810Sbr@bsdpad.com 20210810Sbr@bsdpad.com //Even for a 32 bit process, the ABI says we still need to 20310810Sbr@bsdpad.com //maintain double word alignment of the stack pointer. 20410810Sbr@bsdpad.com uint64_t align = 16; 20510810Sbr@bsdpad.com 20610810Sbr@bsdpad.com // load object file into target memory 20710810Sbr@bsdpad.com objFile->loadSections(initVirtMem); 20810810Sbr@bsdpad.com 20910810Sbr@bsdpad.com enum hardwareCaps 21010810Sbr@bsdpad.com { 21110810Sbr@bsdpad.com M5_HWCAP_SPARC_FLUSH = 1, 21210810Sbr@bsdpad.com M5_HWCAP_SPARC_STBAR = 2, 21310810Sbr@bsdpad.com M5_HWCAP_SPARC_SWAP = 4, 21410810Sbr@bsdpad.com M5_HWCAP_SPARC_MULDIV = 8, 21510810Sbr@bsdpad.com M5_HWCAP_SPARC_V9 = 16, 21610810Sbr@bsdpad.com //This one should technically only be set 21710810Sbr@bsdpad.com //if there is a cheetah or cheetah_plus tlb, 21810810Sbr@bsdpad.com //but we'll use it all the time 21910810Sbr@bsdpad.com M5_HWCAP_SPARC_ULTRA3 = 32 22010810Sbr@bsdpad.com }; 22110810Sbr@bsdpad.com 22210810Sbr@bsdpad.com const int64_t hwcap = 22310810Sbr@bsdpad.com M5_HWCAP_SPARC_FLUSH | 22410810Sbr@bsdpad.com M5_HWCAP_SPARC_STBAR | 22510810Sbr@bsdpad.com M5_HWCAP_SPARC_SWAP | 22610810Sbr@bsdpad.com M5_HWCAP_SPARC_MULDIV | 2276400Sgblack@eecs.umich.edu M5_HWCAP_SPARC_V9 | 22810318Sandreas.hansson@arm.com M5_HWCAP_SPARC_ULTRA3; 2296400Sgblack@eecs.umich.edu 2306400Sgblack@eecs.umich.edu //Setup the auxilliary vectors. These will already have endian conversion. 2316400Sgblack@eecs.umich.edu //Auxilliary vectors are loaded only for elf formatted executables. 2326400Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 2336400Sgblack@eecs.umich.edu if(elfObject) 2346400Sgblack@eecs.umich.edu { 2356400Sgblack@eecs.umich.edu //Bits which describe the system hardware capabilities 23611389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 23711389Sbrandon.potter@amd.com //The system page size 23811389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize)); 23911389Sbrandon.potter@amd.com //Defined to be 100 in the kernel source. 2406400Sgblack@eecs.umich.edu //Frequency at which times() increments 2416400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 2426400Sgblack@eecs.umich.edu // For statically linked executables, this is the virtual address of the 2436400Sgblack@eecs.umich.edu // program header tables if they appear in the executable image 2446400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 2456400Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 2466400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 2476400Sgblack@eecs.umich.edu // This is the number of program headers from the original elf file. 2486400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 2496400Sgblack@eecs.umich.edu //This is the address of the elf "interpreter", It should be set 2506400Sgblack@eecs.umich.edu //to 0 for regular executables. It should be something else 2516400Sgblack@eecs.umich.edu //(not sure what) for dynamic libraries. 2526400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_BASE, 0)); 2536400Sgblack@eecs.umich.edu //This is hardwired to 0 in the elf loading code in the kernel 2546400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 2556400Sgblack@eecs.umich.edu //The entry point to the program 2567414SAli.Saidi@ARM.com auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 2576400Sgblack@eecs.umich.edu //Different user and group IDs 2586400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 2597414SAli.Saidi@ARM.com auxv.push_back(auxv_t(M5_AT_EUID, euid())); 2607414SAli.Saidi@ARM.com auxv.push_back(auxv_t(M5_AT_GID, gid())); 2617414SAli.Saidi@ARM.com auxv.push_back(auxv_t(M5_AT_EGID, egid())); 2626400Sgblack@eecs.umich.edu //Whether to enable "secure mode" in the executable 2636400Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 2646400Sgblack@eecs.umich.edu } 2656400Sgblack@eecs.umich.edu 2666400Sgblack@eecs.umich.edu //Figure out how big the initial stack needs to be 2676400Sgblack@eecs.umich.edu 2686400Sgblack@eecs.umich.edu // The unaccounted for 8 byte 0 at the top of the stack 2696400Sgblack@eecs.umich.edu int sentry_size = 8; 2706400Sgblack@eecs.umich.edu 2716400Sgblack@eecs.umich.edu //This is the name of the file which is present on the initial stack 2726019Shines@cs.fsu.edu //It's purpose is to let the user space linker examine the original file. 2736019Shines@cs.fsu.edu int file_name_size = filename.size() + 1; 2746019Shines@cs.fsu.edu 2756019Shines@cs.fsu.edu int env_data_size = 0; 2766400Sgblack@eecs.umich.edu for (int i = 0; i < envp.size(); ++i) { 2776400Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 2786400Sgblack@eecs.umich.edu } 2797414SAli.Saidi@ARM.com int arg_data_size = 0; 2806400Sgblack@eecs.umich.edu for (int i = 0; i < argv.size(); ++i) { 2816400Sgblack@eecs.umich.edu arg_data_size += argv[i].size() + 1; 2826400Sgblack@eecs.umich.edu } 2836400Sgblack@eecs.umich.edu 2846400Sgblack@eecs.umich.edu //The info_block. 2856400Sgblack@eecs.umich.edu int base_info_block_size = 2866400Sgblack@eecs.umich.edu sentry_size + file_name_size + env_data_size + arg_data_size; 2876400Sgblack@eecs.umich.edu 2886400Sgblack@eecs.umich.edu int info_block_size = roundUp(base_info_block_size, align); 2896400Sgblack@eecs.umich.edu 2906400Sgblack@eecs.umich.edu int info_block_padding = info_block_size - base_info_block_size; 2916400Sgblack@eecs.umich.edu 2926400Sgblack@eecs.umich.edu //Each auxilliary vector is two words 2936400Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 2946400Sgblack@eecs.umich.edu 2956400Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 2966400Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 2976400Sgblack@eecs.umich.edu 2986400Sgblack@eecs.umich.edu int argc_size = intSize; 2996400Sgblack@eecs.umich.edu int window_save_size = intSize * 16; 3006400Sgblack@eecs.umich.edu 3016400Sgblack@eecs.umich.edu //Figure out the size of the contents of the actual initial frame 3026400Sgblack@eecs.umich.edu int frame_size = 3036400Sgblack@eecs.umich.edu aux_array_size + 3046400Sgblack@eecs.umich.edu envp_array_size + 30511886Sbrandon.potter@amd.com argv_array_size + 30611886Sbrandon.potter@amd.com argc_size + 30711886Sbrandon.potter@amd.com window_save_size; 3086400Sgblack@eecs.umich.edu 3096400Sgblack@eecs.umich.edu //There needs to be padding after the auxiliary vector data so that the 31011886Sbrandon.potter@amd.com //very bottom of the stack is aligned properly. 31111886Sbrandon.potter@amd.com int aligned_partial_size = roundUp(frame_size, align); 3126400Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - frame_size; 3136400Sgblack@eecs.umich.edu 31411886Sbrandon.potter@amd.com int space_needed = 31510037SARM gem5 Developers info_block_size + 31610037SARM gem5 Developers aux_padding + 31710037SARM gem5 Developers frame_size; 31810037SARM gem5 Developers 31910037SARM gem5 Developers stack_min = stack_base - space_needed; 32010037SARM gem5 Developers stack_min = roundDown(stack_min, align); 32110037SARM gem5 Developers stack_size = stack_base - stack_min; 32210037SARM gem5 Developers 32310037SARM gem5 Developers // Allocate space for the stack 3246400Sgblack@eecs.umich.edu pTable->allocate(roundDown(stack_min, pageSize), 3256400Sgblack@eecs.umich.edu roundUp(stack_size, pageSize)); 3266400Sgblack@eecs.umich.edu 3276400Sgblack@eecs.umich.edu // map out initial stack contents 3286400Sgblack@eecs.umich.edu IntType sentry_base = stack_base - sentry_size; 3297414SAli.Saidi@ARM.com IntType file_name_base = sentry_base - file_name_size; 3306400Sgblack@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 3316400Sgblack@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 3326400Sgblack@eecs.umich.edu IntType auxv_array_base = arg_data_base - 3336400Sgblack@eecs.umich.edu info_block_padding - aux_array_size - aux_padding; 3346400Sgblack@eecs.umich.edu IntType envp_array_base = auxv_array_base - envp_array_size; 33511886Sbrandon.potter@amd.com IntType argv_array_base = envp_array_base - argv_array_size; 3366400Sgblack@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 3376400Sgblack@eecs.umich.edu#if TRACING_ON 3386400Sgblack@eecs.umich.edu IntType window_save_base = argc_base - window_save_size; 3396400Sgblack@eecs.umich.edu#endif 34010037SARM gem5 Developers 34110037SARM gem5 Developers DPRINTF(Sparc, "The addresses of items on the initial stack:\n"); 3426400Sgblack@eecs.umich.edu DPRINTF(Sparc, "%#x - sentry NULL\n", sentry_base); 3436400Sgblack@eecs.umich.edu DPRINTF(Sparc, "filename = %s\n", filename); 34410037SARM gem5 Developers DPRINTF(Sparc, "%#x - file name\n", file_name_base); 3458852Sandreas.hansson@arm.com DPRINTF(Sparc, "%#x - env data\n", env_data_base); 3466400Sgblack@eecs.umich.edu DPRINTF(Sparc, "%#x - arg data\n", arg_data_base); 3476400Sgblack@eecs.umich.edu DPRINTF(Sparc, "%#x - auxv array\n", auxv_array_base); 3486400Sgblack@eecs.umich.edu DPRINTF(Sparc, "%#x - envp array\n", envp_array_base); 3496400Sgblack@eecs.umich.edu DPRINTF(Sparc, "%#x - argv array\n", argv_array_base); 3506400Sgblack@eecs.umich.edu DPRINTF(Sparc, "%#x - argc \n", argc_base); 3516400Sgblack@eecs.umich.edu DPRINTF(Sparc, "%#x - window save\n", window_save_base); 3528852Sandreas.hansson@arm.com DPRINTF(Sparc, "%#x - stack min\n", stack_min); 3536400Sgblack@eecs.umich.edu 3546400Sgblack@eecs.umich.edu assert(window_save_base == stack_min); 3558852Sandreas.hansson@arm.com 3567414SAli.Saidi@ARM.com // write contents to stack 3577414SAli.Saidi@ARM.com 3587414SAli.Saidi@ARM.com // figure out argc 3596400Sgblack@eecs.umich.edu IntType argc = argv.size(); 3606019Shines@cs.fsu.edu IntType guestArgc = SparcISA::htog(argc); 3616019Shines@cs.fsu.edu 3626400Sgblack@eecs.umich.edu //Write out the sentry void * 36310037SARM gem5 Developers uint64_t sentry_NULL = 0; 3648852Sandreas.hansson@arm.com initVirtMem->writeBlob(sentry_base, 3656400Sgblack@eecs.umich.edu (uint8_t*)&sentry_NULL, sentry_size); 3668852Sandreas.hansson@arm.com 3676400Sgblack@eecs.umich.edu //Write the file name 3686400Sgblack@eecs.umich.edu initVirtMem->writeString(file_name_base, filename.c_str()); 3696400Sgblack@eecs.umich.edu 3706400Sgblack@eecs.umich.edu //Copy the aux stuff 3718852Sandreas.hansson@arm.com for(int x = 0; x < auxv.size(); x++) 3726400Sgblack@eecs.umich.edu { 3736019Shines@cs.fsu.edu initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, 3746400Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 3756400Sgblack@eecs.umich.edu initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 3766019Shines@cs.fsu.edu (uint8_t*)&(auxv[x].a_val), intSize); 3778852Sandreas.hansson@arm.com } 3786019Shines@cs.fsu.edu 3796020Sgblack@eecs.umich.edu //Write out the terminating zeroed auxilliary vector 3806400Sgblack@eecs.umich.edu const IntType zero = 0; 38111886Sbrandon.potter@amd.com initVirtMem->writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 3826400Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3836400Sgblack@eecs.umich.edu initVirtMem->writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 3846400Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3856400Sgblack@eecs.umich.edu 3866400Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 3876400Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 3886400Sgblack@eecs.umich.edu 3896400Sgblack@eecs.umich.edu initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 3906400Sgblack@eecs.umich.edu 3916400Sgblack@eecs.umich.edu //Set up space for the trap handlers into the processes address space. 3926400Sgblack@eecs.umich.edu //Since the stack grows down and there is reserved address space abov 3936400Sgblack@eecs.umich.edu //it, we can put stuff above it and stay out of the way. 3946400Sgblack@eecs.umich.edu fillStart = stack_base; 3956400Sgblack@eecs.umich.edu spillStart = fillStart + sizeof(MachInst) * numFillInsts; 3966400Sgblack@eecs.umich.edu 3976400Sgblack@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 3986019Shines@cs.fsu.edu //Set up the thread context to start running the process 3997720Sgblack@eecs.umich.edu //assert(NumArgumentRegs >= 2); 4007720Sgblack@eecs.umich.edu //tc->setIntReg(ArgumentReg[0], argc); 4017720Sgblack@eecs.umich.edu //tc->setIntReg(ArgumentReg[1], argv_array_base); 40210037SARM gem5 Developers tc->setIntReg(StackPointerReg, stack_min - StackBias); 40310037SARM gem5 Developers 40411389Sbrandon.potter@amd.com // %g1 is a pointer to a function that should be run at exit. Since we 4057720Sgblack@eecs.umich.edu // don't have anything like that, it should be set to 0. 4066400Sgblack@eecs.umich.edu tc->setIntReg(1, 0); 40711886Sbrandon.potter@amd.com 40811886Sbrandon.potter@amd.com Addr prog_entry = objFile->entryPoint(); 4096019Shines@cs.fsu.edu tc->setPC(prog_entry); 4106019Shines@cs.fsu.edu tc->setNextPC(prog_entry + sizeof(MachInst)); 4116020Sgblack@eecs.umich.edu tc->setNextNPC(prog_entry + (2 * sizeof(MachInst))); 41211851Sbrandon.potter@amd.com 4136020Sgblack@eecs.umich.edu //Align the "stack_min" to a page boundary. 4147441SAli.Saidi@ARM.com stack_min = roundDown(stack_min, pageSize); 4156701Sgblack@eecs.umich.edu 4166020Sgblack@eecs.umich.edu// num_processes++; 4176020Sgblack@eecs.umich.edu} 41810037SARM gem5 Developers 41911851Sbrandon.potter@amd.comvoid 42010037SARM gem5 DevelopersSparc64LiveProcess::argsInit(int intSize, int pageSize) 42110037SARM gem5 Developers{ 42210037SARM gem5 Developers SparcLiveProcess::argsInit<uint64_t>(pageSize); 42310037SARM gem5 Developers 42410037SARM gem5 Developers // Stuff the trap handlers into the process address space 42510037SARM gem5 Developers initVirtMem->writeBlob(fillStart, 42611851Sbrandon.potter@amd.com (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 4277441SAli.Saidi@ARM.com initVirtMem->writeBlob(spillStart, 4287441SAli.Saidi@ARM.com (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 4297441SAli.Saidi@ARM.com} 4307441SAli.Saidi@ARM.com 4317441SAli.Saidi@ARM.comvoid 4327441SAli.Saidi@ARM.comSparc32LiveProcess::argsInit(int intSize, int pageSize) 4337441SAli.Saidi@ARM.com{ 4347441SAli.Saidi@ARM.com SparcLiveProcess::argsInit<uint32_t>(pageSize); 4357441SAli.Saidi@ARM.com 4367441SAli.Saidi@ARM.com // Stuff the trap handlers into the process address space 4377441SAli.Saidi@ARM.com initVirtMem->writeBlob(fillStart, 4387441SAli.Saidi@ARM.com (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 4397441SAli.Saidi@ARM.com initVirtMem->writeBlob(spillStart, 4407441SAli.Saidi@ARM.com (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 4417441SAli.Saidi@ARM.com} 4427441SAli.Saidi@ARM.com 4437441SAli.Saidi@ARM.comvoid Sparc32LiveProcess::flushWindows(ThreadContext *tc) 44410037SARM gem5 Developers{ 44511851Sbrandon.potter@amd.com IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 44610037SARM gem5 Developers IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 44710037SARM gem5 Developers IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 44810037SARM gem5 Developers MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 44910037SARM gem5 Developers MiscReg origCWP = CWP; 4507441SAli.Saidi@ARM.com CWP = (CWP + Cansave + 2) % NWindows; 4516020Sgblack@eecs.umich.edu while(NWindows - 2 - Cansave != 0) 45211851Sbrandon.potter@amd.com { 4536020Sgblack@eecs.umich.edu if (Otherwin) { 45410037SARM gem5 Developers panic("Otherwin non-zero.\n"); 4556020Sgblack@eecs.umich.edu } else { 4566020Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4576020Sgblack@eecs.umich.edu //Do the stores 4586020Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 45911851Sbrandon.potter@amd.com for (int index = 16; index < 32; index++) { 46010037SARM gem5 Developers uint32_t regVal = tc->readIntReg(index); 46110037SARM gem5 Developers regVal = htog(regVal); 46210037SARM gem5 Developers if (!tc->getMemPort()->tryWriteBlob( 46310037SARM gem5 Developers sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 46410037SARM gem5 Developers warn("Failed to save register to the stack when " 46510037SARM gem5 Developers "flushing windows.\n"); 46611851Sbrandon.potter@amd.com } 4676020Sgblack@eecs.umich.edu } 46810810Sbr@bsdpad.com Canrestore--; 46910810Sbr@bsdpad.com Cansave++; 47010810Sbr@bsdpad.com CWP = (CWP + 1) % NWindows; 47110810Sbr@bsdpad.com } 47210810Sbr@bsdpad.com } 47310810Sbr@bsdpad.com tc->setIntReg(NumIntArchRegs + 3, Cansave); 47410810Sbr@bsdpad.com tc->setIntReg(NumIntArchRegs + 4, Canrestore); 47510810Sbr@bsdpad.com tc->setMiscReg(MISCREG_CWP, origCWP); 47610810Sbr@bsdpad.com} 47710810Sbr@bsdpad.com 47810810Sbr@bsdpad.comvoid Sparc64LiveProcess::flushWindows(ThreadContext *tc) 47910223Ssteve.reinhardt@amd.com{ 4806020Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 48110037SARM gem5 Developers IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 48210037SARM gem5 Developers IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 48311851Sbrandon.potter@amd.com MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 48410037SARM gem5 Developers MiscReg origCWP = CWP; 48510810Sbr@bsdpad.com CWP = (CWP + Cansave + 2) % NWindows; 48610810Sbr@bsdpad.com while(NWindows - 2 - Cansave != 0) 48710810Sbr@bsdpad.com { 48810810Sbr@bsdpad.com if (Otherwin) { 48910810Sbr@bsdpad.com panic("Otherwin non-zero.\n"); 49010810Sbr@bsdpad.com } else { 49110810Sbr@bsdpad.com tc->setMiscReg(MISCREG_CWP, CWP); 49210810Sbr@bsdpad.com //Do the stores 49310810Sbr@bsdpad.com IntReg sp = tc->readIntReg(StackPointerReg); 49410810Sbr@bsdpad.com for (int index = 16; index < 32; index++) { 49510810Sbr@bsdpad.com IntReg regVal = tc->readIntReg(index); 49610223Ssteve.reinhardt@amd.com regVal = htog(regVal); 49710037SARM gem5 Developers if (!tc->getMemPort()->tryWriteBlob( 498 sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 499 warn("Failed to save register to the stack when " 500 "flushing windows.\n"); 501 } 502 } 503 Canrestore--; 504 Cansave++; 505 CWP = (CWP + 1) % NWindows; 506 } 507 } 508 tc->setIntReg(NumIntArchRegs + 3, Cansave); 509 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 510 tc->setMiscReg(MISCREG_CWP, origCWP); 511} 512