process.cc revision 11886:43b882cada33
1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#include "arch/sparc/process.hh" 33 34#include "arch/sparc/asi.hh" 35#include "arch/sparc/handlers.hh" 36#include "arch/sparc/isa_traits.hh" 37#include "arch/sparc/registers.hh" 38#include "arch/sparc/types.hh" 39#include "base/loader/elf_object.hh" 40#include "base/loader/object_file.hh" 41#include "base/misc.hh" 42#include "cpu/thread_context.hh" 43#include "debug/Stack.hh" 44#include "mem/page_table.hh" 45#include "sim/aux_vector.hh" 46#include "sim/process_impl.hh" 47#include "sim/syscall_return.hh" 48#include "sim/system.hh" 49 50using namespace std; 51using namespace SparcISA; 52 53static const int FirstArgumentReg = 8; 54 55 56SparcProcess::SparcProcess(ProcessParams * params, ObjectFile *objFile, 57 Addr _StackBias) 58 : Process(params, objFile), StackBias(_StackBias) 59{ 60 61 // XXX all the below need to be updated for SPARC - Ali 62 memState->brkPoint = objFile->dataBase() + objFile->dataSize() + 63 objFile->bssSize(); 64 memState->brkPoint = roundUp(memState->brkPoint, PageBytes); 65 66 // Set pointer for next thread stack. Reserve 8M for main stack. 67 memState->nextThreadStackBase = memState->stackBase - (8 * 1024 * 1024); 68 69 // Initialize these to 0s 70 fillStart = 0; 71 spillStart = 0; 72} 73 74void 75SparcProcess::handleTrap(int trapNum, ThreadContext *tc, Fault *fault) 76{ 77 PCState pc = tc->pcState(); 78 switch (trapNum) { 79 case 0x01: // Software breakpoint 80 warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 81 break; 82 case 0x02: // Division by zero 83 warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 84 break; 85 case 0x03: // Flush window trap 86 flushWindows(tc); 87 break; 88 case 0x04: // Clean windows 89 warn("Ignoring process request for clean register " 90 "windows at pc %#x.\n", pc.pc()); 91 break; 92 case 0x05: // Range check 93 warn("Software signaled a range check at pc %#x.\n", pc.pc()); 94 break; 95 case 0x06: // Fix alignment 96 warn("Ignoring process request for os assisted unaligned accesses " 97 "at pc %#x.\n", pc.pc()); 98 break; 99 case 0x07: // Integer overflow 100 warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 101 break; 102 case 0x32: // Get integer condition codes 103 warn("Ignoring process request to get the integer condition codes " 104 "at pc %#x.\n", pc.pc()); 105 break; 106 case 0x33: // Set integer condition codes 107 warn("Ignoring process request to set the integer condition codes " 108 "at pc %#x.\n", pc.pc()); 109 break; 110 default: 111 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 112 } 113} 114 115void 116SparcProcess::initState() 117{ 118 Process::initState(); 119 120 ThreadContext *tc = system->getThreadContext(contextIds[0]); 121 // From the SPARC ABI 122 123 // Setup default FP state 124 tc->setMiscRegNoEffect(MISCREG_FSR, 0); 125 126 tc->setMiscRegNoEffect(MISCREG_TICK, 0); 127 128 /* 129 * Register window management registers 130 */ 131 132 // No windows contain info from other programs 133 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 134 tc->setIntReg(NumIntArchRegs + 6, 0); 135 // There are no windows to pop 136 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 137 tc->setIntReg(NumIntArchRegs + 4, 0); 138 // All windows are available to save into 139 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 140 tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 141 // All windows are "clean" 142 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 143 tc->setIntReg(NumIntArchRegs + 5, NWindows); 144 // Start with register window 0 145 tc->setMiscReg(MISCREG_CWP, 0); 146 // Always use spill and fill traps 0 147 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 148 tc->setIntReg(NumIntArchRegs + 7, 0); 149 // Set the trap level to 0 150 tc->setMiscRegNoEffect(MISCREG_TL, 0); 151 // Set the ASI register to something fixed 152 tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 153 154 // Set the MMU Primary Context Register to hold the process' pid 155 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, _pid); 156 157 /* 158 * T1 specific registers 159 */ 160 // Turn on the icache, dcache, dtb translation, and itb translation. 161 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 162} 163 164void 165Sparc32Process::initState() 166{ 167 SparcProcess::initState(); 168 169 ThreadContext *tc = system->getThreadContext(contextIds[0]); 170 // The process runs in user mode with 32 bit addresses 171 PSTATE pstate = 0; 172 pstate.ie = 1; 173 pstate.am = 1; 174 tc->setMiscReg(MISCREG_PSTATE, pstate); 175 176 argsInit(32 / 8, PageBytes); 177} 178 179void 180Sparc64Process::initState() 181{ 182 SparcProcess::initState(); 183 184 ThreadContext *tc = system->getThreadContext(contextIds[0]); 185 // The process runs in user mode 186 PSTATE pstate = 0; 187 pstate.ie = 1; 188 tc->setMiscReg(MISCREG_PSTATE, pstate); 189 190 argsInit(sizeof(IntReg), PageBytes); 191} 192 193template<class IntType> 194void 195SparcProcess::argsInit(int pageSize) 196{ 197 int intSize = sizeof(IntType); 198 199 typedef AuxVector<IntType> auxv_t; 200 201 std::vector<auxv_t> auxv; 202 203 string filename; 204 if (argv.size() < 1) 205 filename = ""; 206 else 207 filename = argv[0]; 208 209 // Even for a 32 bit process, the ABI says we still need to 210 // maintain double word alignment of the stack pointer. 211 uint64_t align = 16; 212 213 // Patch the ld_bias for dynamic executables. 214 updateBias(); 215 216 // load object file into target memory 217 objFile->loadSections(initVirtMem); 218 219 enum hardwareCaps 220 { 221 M5_HWCAP_SPARC_FLUSH = 1, 222 M5_HWCAP_SPARC_STBAR = 2, 223 M5_HWCAP_SPARC_SWAP = 4, 224 M5_HWCAP_SPARC_MULDIV = 8, 225 M5_HWCAP_SPARC_V9 = 16, 226 // This one should technically only be set 227 // if there is a cheetah or cheetah_plus tlb, 228 // but we'll use it all the time 229 M5_HWCAP_SPARC_ULTRA3 = 32 230 }; 231 232 const int64_t hwcap = 233 M5_HWCAP_SPARC_FLUSH | 234 M5_HWCAP_SPARC_STBAR | 235 M5_HWCAP_SPARC_SWAP | 236 M5_HWCAP_SPARC_MULDIV | 237 M5_HWCAP_SPARC_V9 | 238 M5_HWCAP_SPARC_ULTRA3; 239 240 // Setup the auxilliary vectors. These will already have endian conversion. 241 // Auxilliary vectors are loaded only for elf formatted executables. 242 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 243 if (elfObject) { 244 // Bits which describe the system hardware capabilities 245 auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 246 // The system page size 247 auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::PageBytes)); 248 // Defined to be 100 in the kernel source. 249 // Frequency at which times() increments 250 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 251 // For statically linked executables, this is the virtual address of the 252 // program header tables if they appear in the executable image 253 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 254 // This is the size of a program header entry from the elf file. 255 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 256 // This is the number of program headers from the original elf file. 257 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 258 // This is the base address of the ELF interpreter; it should be 259 // zero for static executables or contain the base address for 260 // dynamic executables. 261 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 262 // This is hardwired to 0 in the elf loading code in the kernel 263 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 264 // The entry point to the program 265 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 266 // Different user and group IDs 267 auxv.push_back(auxv_t(M5_AT_UID, uid())); 268 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 269 auxv.push_back(auxv_t(M5_AT_GID, gid())); 270 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 271 // Whether to enable "secure mode" in the executable 272 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 273 } 274 275 // Figure out how big the initial stack needs to be 276 277 // The unaccounted for 8 byte 0 at the top of the stack 278 int sentry_size = 8; 279 280 // This is the name of the file which is present on the initial stack 281 // It's purpose is to let the user space linker examine the original file. 282 int file_name_size = filename.size() + 1; 283 284 int env_data_size = 0; 285 for (int i = 0; i < envp.size(); ++i) { 286 env_data_size += envp[i].size() + 1; 287 } 288 int arg_data_size = 0; 289 for (int i = 0; i < argv.size(); ++i) { 290 arg_data_size += argv[i].size() + 1; 291 } 292 293 // The info_block. 294 int base_info_block_size = 295 sentry_size + file_name_size + env_data_size + arg_data_size; 296 297 int info_block_size = roundUp(base_info_block_size, align); 298 299 int info_block_padding = info_block_size - base_info_block_size; 300 301 // Each auxilliary vector is two words 302 int aux_array_size = intSize * 2 * (auxv.size() + 1); 303 304 int envp_array_size = intSize * (envp.size() + 1); 305 int argv_array_size = intSize * (argv.size() + 1); 306 307 int argc_size = intSize; 308 int window_save_size = intSize * 16; 309 310 // Figure out the size of the contents of the actual initial frame 311 int frame_size = 312 aux_array_size + 313 envp_array_size + 314 argv_array_size + 315 argc_size + 316 window_save_size; 317 318 // There needs to be padding after the auxiliary vector data so that the 319 // very bottom of the stack is aligned properly. 320 int aligned_partial_size = roundUp(frame_size, align); 321 int aux_padding = aligned_partial_size - frame_size; 322 323 int space_needed = 324 info_block_size + 325 aux_padding + 326 frame_size; 327 328 memState->stackMin = memState->stackBase - space_needed; 329 memState->stackMin = roundDown(memState->stackMin, align); 330 memState->stackSize = memState->stackBase - memState->stackMin; 331 332 // Allocate space for the stack 333 allocateMem(roundDown(memState->stackMin, pageSize), 334 roundUp(memState->stackSize, pageSize)); 335 336 // map out initial stack contents 337 IntType sentry_base = memState->stackBase - sentry_size; 338 IntType file_name_base = sentry_base - file_name_size; 339 IntType env_data_base = file_name_base - env_data_size; 340 IntType arg_data_base = env_data_base - arg_data_size; 341 IntType auxv_array_base = arg_data_base - 342 info_block_padding - aux_array_size - aux_padding; 343 IntType envp_array_base = auxv_array_base - envp_array_size; 344 IntType argv_array_base = envp_array_base - argv_array_size; 345 IntType argc_base = argv_array_base - argc_size; 346#if TRACING_ON 347 IntType window_save_base = argc_base - window_save_size; 348#endif 349 350 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 351 DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 352 DPRINTF(Stack, "filename = %s\n", filename); 353 DPRINTF(Stack, "%#x - file name\n", file_name_base); 354 DPRINTF(Stack, "%#x - env data\n", env_data_base); 355 DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 356 DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 357 DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 358 DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 359 DPRINTF(Stack, "%#x - argc \n", argc_base); 360 DPRINTF(Stack, "%#x - window save\n", window_save_base); 361 DPRINTF(Stack, "%#x - stack min\n", memState->stackMin); 362 363 assert(window_save_base == memState->stackMin); 364 365 // write contents to stack 366 367 // figure out argc 368 IntType argc = argv.size(); 369 IntType guestArgc = SparcISA::htog(argc); 370 371 // Write out the sentry void * 372 uint64_t sentry_NULL = 0; 373 initVirtMem.writeBlob(sentry_base, 374 (uint8_t*)&sentry_NULL, sentry_size); 375 376 // Write the file name 377 initVirtMem.writeString(file_name_base, filename.c_str()); 378 379 // Copy the aux stuff 380 for (int x = 0; x < auxv.size(); x++) { 381 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 382 (uint8_t*)&(auxv[x].a_type), intSize); 383 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 384 (uint8_t*)&(auxv[x].a_val), intSize); 385 } 386 387 // Write out the terminating zeroed auxilliary vector 388 const IntType zero = 0; 389 initVirtMem.writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 390 (uint8_t*)&zero, intSize); 391 initVirtMem.writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 392 (uint8_t*)&zero, intSize); 393 394 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 395 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 396 397 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 398 399 // Set up space for the trap handlers into the processes address space. 400 // Since the stack grows down and there is reserved address space abov 401 // it, we can put stuff above it and stay out of the way. 402 fillStart = memState->stackBase; 403 spillStart = fillStart + sizeof(MachInst) * numFillInsts; 404 405 ThreadContext *tc = system->getThreadContext(contextIds[0]); 406 // Set up the thread context to start running the process 407 // assert(NumArgumentRegs >= 2); 408 // tc->setIntReg(ArgumentReg[0], argc); 409 // tc->setIntReg(ArgumentReg[1], argv_array_base); 410 tc->setIntReg(StackPointerReg, memState->stackMin - StackBias); 411 412 // %g1 is a pointer to a function that should be run at exit. Since we 413 // don't have anything like that, it should be set to 0. 414 tc->setIntReg(1, 0); 415 416 tc->pcState(getStartPC()); 417 418 // Align the "stack_min" to a page boundary. 419 memState->stackMin = roundDown(memState->stackMin, pageSize); 420} 421 422void 423Sparc64Process::argsInit(int intSize, int pageSize) 424{ 425 SparcProcess::argsInit<uint64_t>(pageSize); 426 427 // Stuff the trap handlers into the process address space 428 initVirtMem.writeBlob(fillStart, 429 (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 430 initVirtMem.writeBlob(spillStart, 431 (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 432} 433 434void 435Sparc32Process::argsInit(int intSize, int pageSize) 436{ 437 SparcProcess::argsInit<uint32_t>(pageSize); 438 439 // Stuff the trap handlers into the process address space 440 initVirtMem.writeBlob(fillStart, 441 (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 442 initVirtMem.writeBlob(spillStart, 443 (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 444} 445 446void Sparc32Process::flushWindows(ThreadContext *tc) 447{ 448 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 449 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 450 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 451 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 452 MiscReg origCWP = CWP; 453 CWP = (CWP + Cansave + 2) % NWindows; 454 while (NWindows - 2 - Cansave != 0) { 455 if (Otherwin) { 456 panic("Otherwin non-zero.\n"); 457 } else { 458 tc->setMiscReg(MISCREG_CWP, CWP); 459 // Do the stores 460 IntReg sp = tc->readIntReg(StackPointerReg); 461 for (int index = 16; index < 32; index++) { 462 uint32_t regVal = tc->readIntReg(index); 463 regVal = htog(regVal); 464 if (!tc->getMemProxy().tryWriteBlob( 465 sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 466 warn("Failed to save register to the stack when " 467 "flushing windows.\n"); 468 } 469 } 470 Canrestore--; 471 Cansave++; 472 CWP = (CWP + 1) % NWindows; 473 } 474 } 475 tc->setIntReg(NumIntArchRegs + 3, Cansave); 476 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 477 tc->setMiscReg(MISCREG_CWP, origCWP); 478} 479 480void 481Sparc64Process::flushWindows(ThreadContext *tc) 482{ 483 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 484 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 485 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 486 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 487 MiscReg origCWP = CWP; 488 CWP = (CWP + Cansave + 2) % NWindows; 489 while (NWindows - 2 - Cansave != 0) { 490 if (Otherwin) { 491 panic("Otherwin non-zero.\n"); 492 } else { 493 tc->setMiscReg(MISCREG_CWP, CWP); 494 // Do the stores 495 IntReg sp = tc->readIntReg(StackPointerReg); 496 for (int index = 16; index < 32; index++) { 497 IntReg regVal = tc->readIntReg(index); 498 regVal = htog(regVal); 499 if (!tc->getMemProxy().tryWriteBlob( 500 sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 501 warn("Failed to save register to the stack when " 502 "flushing windows.\n"); 503 } 504 } 505 Canrestore--; 506 Cansave++; 507 CWP = (CWP + 1) % NWindows; 508 } 509 } 510 tc->setIntReg(NumIntArchRegs + 3, Cansave); 511 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 512 tc->setMiscReg(MISCREG_CWP, origCWP); 513} 514 515IntReg 516Sparc32Process::getSyscallArg(ThreadContext *tc, int &i) 517{ 518 assert(i < 6); 519 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 520} 521 522void 523Sparc32Process::setSyscallArg(ThreadContext *tc, int i, IntReg val) 524{ 525 assert(i < 6); 526 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 527} 528 529IntReg 530Sparc64Process::getSyscallArg(ThreadContext *tc, int &i) 531{ 532 assert(i < 6); 533 return tc->readIntReg(FirstArgumentReg + i++); 534} 535 536void 537Sparc64Process::setSyscallArg(ThreadContext *tc, int i, IntReg val) 538{ 539 assert(i < 6); 540 tc->setIntReg(FirstArgumentReg + i, val); 541} 542 543void 544SparcProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 545{ 546 // check for error condition. SPARC syscall convention is to 547 // indicate success/failure in reg the carry bit of the ccr 548 // and put the return value itself in the standard return value reg (). 549 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 550 if (sysret.successful()) { 551 // no error, clear XCC.C 552 tc->setIntReg(NumIntArchRegs + 2, 553 tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 554 IntReg val = sysret.returnValue(); 555 if (pstate.am) 556 val = bits(val, 31, 0); 557 tc->setIntReg(ReturnValueReg, val); 558 } else { 559 // got an error, set XCC.C 560 tc->setIntReg(NumIntArchRegs + 2, 561 tc->readIntReg(NumIntArchRegs + 2) | 0x11); 562 IntReg val = sysret.errnoValue(); 563 if (pstate.am) 564 val = bits(val, 31, 0); 565 tc->setIntReg(ReturnValueReg, val); 566 } 567} 568