process.cc revision 11854
1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#include "arch/sparc/process.hh" 33 34#include "arch/sparc/asi.hh" 35#include "arch/sparc/handlers.hh" 36#include "arch/sparc/isa_traits.hh" 37#include "arch/sparc/registers.hh" 38#include "arch/sparc/types.hh" 39#include "base/loader/elf_object.hh" 40#include "base/loader/object_file.hh" 41#include "base/misc.hh" 42#include "cpu/thread_context.hh" 43#include "debug/Stack.hh" 44#include "mem/page_table.hh" 45#include "sim/aux_vector.hh" 46#include "sim/process_impl.hh" 47#include "sim/syscall_return.hh" 48#include "sim/system.hh" 49 50using namespace std; 51using namespace SparcISA; 52 53static const int FirstArgumentReg = 8; 54 55 56SparcProcess::SparcProcess(ProcessParams * params, ObjectFile *objFile, 57 Addr _StackBias) 58 : Process(params, objFile), StackBias(_StackBias) 59{ 60 61 // XXX all the below need to be updated for SPARC - Ali 62 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 63 brk_point = roundUp(brk_point, PageBytes); 64 65 // Set pointer for next thread stack. Reserve 8M for main stack. 66 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 67 68 // Initialize these to 0s 69 fillStart = 0; 70 spillStart = 0; 71} 72 73void 74SparcProcess::handleTrap(int trapNum, ThreadContext *tc) 75{ 76 PCState pc = tc->pcState(); 77 switch (trapNum) { 78 case 0x01: // Software breakpoint 79 warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 80 break; 81 case 0x02: // Division by zero 82 warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 83 break; 84 case 0x03: // Flush window trap 85 flushWindows(tc); 86 break; 87 case 0x04: // Clean windows 88 warn("Ignoring process request for clean register " 89 "windows at pc %#x.\n", pc.pc()); 90 break; 91 case 0x05: // Range check 92 warn("Software signaled a range check at pc %#x.\n", pc.pc()); 93 break; 94 case 0x06: // Fix alignment 95 warn("Ignoring process request for os assisted unaligned accesses " 96 "at pc %#x.\n", pc.pc()); 97 break; 98 case 0x07: // Integer overflow 99 warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 100 break; 101 case 0x32: // Get integer condition codes 102 warn("Ignoring process request to get the integer condition codes " 103 "at pc %#x.\n", pc.pc()); 104 break; 105 case 0x33: // Set integer condition codes 106 warn("Ignoring process request to set the integer condition codes " 107 "at pc %#x.\n", pc.pc()); 108 break; 109 default: 110 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 111 } 112} 113 114void 115SparcProcess::initState() 116{ 117 Process::initState(); 118 119 ThreadContext *tc = system->getThreadContext(contextIds[0]); 120 // From the SPARC ABI 121 122 // Setup default FP state 123 tc->setMiscRegNoEffect(MISCREG_FSR, 0); 124 125 tc->setMiscRegNoEffect(MISCREG_TICK, 0); 126 127 /* 128 * Register window management registers 129 */ 130 131 // No windows contain info from other programs 132 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 133 tc->setIntReg(NumIntArchRegs + 6, 0); 134 // There are no windows to pop 135 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 136 tc->setIntReg(NumIntArchRegs + 4, 0); 137 // All windows are available to save into 138 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 139 tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 140 // All windows are "clean" 141 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 142 tc->setIntReg(NumIntArchRegs + 5, NWindows); 143 // Start with register window 0 144 tc->setMiscReg(MISCREG_CWP, 0); 145 // Always use spill and fill traps 0 146 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 147 tc->setIntReg(NumIntArchRegs + 7, 0); 148 // Set the trap level to 0 149 tc->setMiscRegNoEffect(MISCREG_TL, 0); 150 // Set the ASI register to something fixed 151 tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 152 153 // Set the MMU Primary Context Register to hold the process' pid 154 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, _pid); 155 156 /* 157 * T1 specific registers 158 */ 159 // Turn on the icache, dcache, dtb translation, and itb translation. 160 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 161} 162 163void 164Sparc32Process::initState() 165{ 166 SparcProcess::initState(); 167 168 ThreadContext *tc = system->getThreadContext(contextIds[0]); 169 // The process runs in user mode with 32 bit addresses 170 PSTATE pstate = 0; 171 pstate.ie = 1; 172 pstate.am = 1; 173 tc->setMiscReg(MISCREG_PSTATE, pstate); 174 175 argsInit(32 / 8, PageBytes); 176} 177 178void 179Sparc64Process::initState() 180{ 181 SparcProcess::initState(); 182 183 ThreadContext *tc = system->getThreadContext(contextIds[0]); 184 // The process runs in user mode 185 PSTATE pstate = 0; 186 pstate.ie = 1; 187 tc->setMiscReg(MISCREG_PSTATE, pstate); 188 189 argsInit(sizeof(IntReg), PageBytes); 190} 191 192template<class IntType> 193void 194SparcProcess::argsInit(int pageSize) 195{ 196 int intSize = sizeof(IntType); 197 198 typedef AuxVector<IntType> auxv_t; 199 200 std::vector<auxv_t> auxv; 201 202 string filename; 203 if (argv.size() < 1) 204 filename = ""; 205 else 206 filename = argv[0]; 207 208 // Even for a 32 bit process, the ABI says we still need to 209 // maintain double word alignment of the stack pointer. 210 uint64_t align = 16; 211 212 // Patch the ld_bias for dynamic executables. 213 updateBias(); 214 215 // load object file into target memory 216 objFile->loadSections(initVirtMem); 217 218 enum hardwareCaps 219 { 220 M5_HWCAP_SPARC_FLUSH = 1, 221 M5_HWCAP_SPARC_STBAR = 2, 222 M5_HWCAP_SPARC_SWAP = 4, 223 M5_HWCAP_SPARC_MULDIV = 8, 224 M5_HWCAP_SPARC_V9 = 16, 225 // This one should technically only be set 226 // if there is a cheetah or cheetah_plus tlb, 227 // but we'll use it all the time 228 M5_HWCAP_SPARC_ULTRA3 = 32 229 }; 230 231 const int64_t hwcap = 232 M5_HWCAP_SPARC_FLUSH | 233 M5_HWCAP_SPARC_STBAR | 234 M5_HWCAP_SPARC_SWAP | 235 M5_HWCAP_SPARC_MULDIV | 236 M5_HWCAP_SPARC_V9 | 237 M5_HWCAP_SPARC_ULTRA3; 238 239 // Setup the auxilliary vectors. These will already have endian conversion. 240 // Auxilliary vectors are loaded only for elf formatted executables. 241 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 242 if (elfObject) { 243 // Bits which describe the system hardware capabilities 244 auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 245 // The system page size 246 auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::PageBytes)); 247 // Defined to be 100 in the kernel source. 248 // Frequency at which times() increments 249 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 250 // For statically linked executables, this is the virtual address of the 251 // program header tables if they appear in the executable image 252 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 253 // This is the size of a program header entry from the elf file. 254 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 255 // This is the number of program headers from the original elf file. 256 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 257 // This is the base address of the ELF interpreter; it should be 258 // zero for static executables or contain the base address for 259 // dynamic executables. 260 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 261 // This is hardwired to 0 in the elf loading code in the kernel 262 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 263 // The entry point to the program 264 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 265 // Different user and group IDs 266 auxv.push_back(auxv_t(M5_AT_UID, uid())); 267 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 268 auxv.push_back(auxv_t(M5_AT_GID, gid())); 269 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 270 // Whether to enable "secure mode" in the executable 271 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 272 } 273 274 // Figure out how big the initial stack needs to be 275 276 // The unaccounted for 8 byte 0 at the top of the stack 277 int sentry_size = 8; 278 279 // This is the name of the file which is present on the initial stack 280 // It's purpose is to let the user space linker examine the original file. 281 int file_name_size = filename.size() + 1; 282 283 int env_data_size = 0; 284 for (int i = 0; i < envp.size(); ++i) { 285 env_data_size += envp[i].size() + 1; 286 } 287 int arg_data_size = 0; 288 for (int i = 0; i < argv.size(); ++i) { 289 arg_data_size += argv[i].size() + 1; 290 } 291 292 // The info_block. 293 int base_info_block_size = 294 sentry_size + file_name_size + env_data_size + arg_data_size; 295 296 int info_block_size = roundUp(base_info_block_size, align); 297 298 int info_block_padding = info_block_size - base_info_block_size; 299 300 // Each auxilliary vector is two words 301 int aux_array_size = intSize * 2 * (auxv.size() + 1); 302 303 int envp_array_size = intSize * (envp.size() + 1); 304 int argv_array_size = intSize * (argv.size() + 1); 305 306 int argc_size = intSize; 307 int window_save_size = intSize * 16; 308 309 // Figure out the size of the contents of the actual initial frame 310 int frame_size = 311 aux_array_size + 312 envp_array_size + 313 argv_array_size + 314 argc_size + 315 window_save_size; 316 317 // There needs to be padding after the auxiliary vector data so that the 318 // very bottom of the stack is aligned properly. 319 int aligned_partial_size = roundUp(frame_size, align); 320 int aux_padding = aligned_partial_size - frame_size; 321 322 int space_needed = 323 info_block_size + 324 aux_padding + 325 frame_size; 326 327 stack_min = stack_base - space_needed; 328 stack_min = roundDown(stack_min, align); 329 stack_size = stack_base - stack_min; 330 331 // Allocate space for the stack 332 allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); 333 334 // map out initial stack contents 335 IntType sentry_base = stack_base - sentry_size; 336 IntType file_name_base = sentry_base - file_name_size; 337 IntType env_data_base = file_name_base - env_data_size; 338 IntType arg_data_base = env_data_base - arg_data_size; 339 IntType auxv_array_base = arg_data_base - 340 info_block_padding - aux_array_size - aux_padding; 341 IntType envp_array_base = auxv_array_base - envp_array_size; 342 IntType argv_array_base = envp_array_base - argv_array_size; 343 IntType argc_base = argv_array_base - argc_size; 344#if TRACING_ON 345 IntType window_save_base = argc_base - window_save_size; 346#endif 347 348 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 349 DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 350 DPRINTF(Stack, "filename = %s\n", filename); 351 DPRINTF(Stack, "%#x - file name\n", file_name_base); 352 DPRINTF(Stack, "%#x - env data\n", env_data_base); 353 DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 354 DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 355 DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 356 DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 357 DPRINTF(Stack, "%#x - argc \n", argc_base); 358 DPRINTF(Stack, "%#x - window save\n", window_save_base); 359 DPRINTF(Stack, "%#x - stack min\n", stack_min); 360 361 assert(window_save_base == stack_min); 362 363 // write contents to stack 364 365 // figure out argc 366 IntType argc = argv.size(); 367 IntType guestArgc = SparcISA::htog(argc); 368 369 // Write out the sentry void * 370 uint64_t sentry_NULL = 0; 371 initVirtMem.writeBlob(sentry_base, 372 (uint8_t*)&sentry_NULL, sentry_size); 373 374 // Write the file name 375 initVirtMem.writeString(file_name_base, filename.c_str()); 376 377 // Copy the aux stuff 378 for (int x = 0; x < auxv.size(); x++) { 379 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 380 (uint8_t*)&(auxv[x].a_type), intSize); 381 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 382 (uint8_t*)&(auxv[x].a_val), intSize); 383 } 384 385 // Write out the terminating zeroed auxilliary vector 386 const IntType zero = 0; 387 initVirtMem.writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 388 (uint8_t*)&zero, intSize); 389 initVirtMem.writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 390 (uint8_t*)&zero, intSize); 391 392 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 393 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 394 395 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 396 397 // Set up space for the trap handlers into the processes address space. 398 // Since the stack grows down and there is reserved address space abov 399 // it, we can put stuff above it and stay out of the way. 400 fillStart = stack_base; 401 spillStart = fillStart + sizeof(MachInst) * numFillInsts; 402 403 ThreadContext *tc = system->getThreadContext(contextIds[0]); 404 // Set up the thread context to start running the process 405 // assert(NumArgumentRegs >= 2); 406 // tc->setIntReg(ArgumentReg[0], argc); 407 // tc->setIntReg(ArgumentReg[1], argv_array_base); 408 tc->setIntReg(StackPointerReg, stack_min - StackBias); 409 410 // %g1 is a pointer to a function that should be run at exit. Since we 411 // don't have anything like that, it should be set to 0. 412 tc->setIntReg(1, 0); 413 414 tc->pcState(getStartPC()); 415 416 // Align the "stack_min" to a page boundary. 417 stack_min = roundDown(stack_min, pageSize); 418 419// num_processes++; 420} 421 422void 423Sparc64Process::argsInit(int intSize, int pageSize) 424{ 425 SparcProcess::argsInit<uint64_t>(pageSize); 426 427 // Stuff the trap handlers into the process address space 428 initVirtMem.writeBlob(fillStart, 429 (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 430 initVirtMem.writeBlob(spillStart, 431 (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 432} 433 434void 435Sparc32Process::argsInit(int intSize, int pageSize) 436{ 437 SparcProcess::argsInit<uint32_t>(pageSize); 438 439 // Stuff the trap handlers into the process address space 440 initVirtMem.writeBlob(fillStart, 441 (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 442 initVirtMem.writeBlob(spillStart, 443 (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 444} 445 446void Sparc32Process::flushWindows(ThreadContext *tc) 447{ 448 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 449 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 450 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 451 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 452 MiscReg origCWP = CWP; 453 CWP = (CWP + Cansave + 2) % NWindows; 454 while (NWindows - 2 - Cansave != 0) { 455 if (Otherwin) { 456 panic("Otherwin non-zero.\n"); 457 } else { 458 tc->setMiscReg(MISCREG_CWP, CWP); 459 // Do the stores 460 IntReg sp = tc->readIntReg(StackPointerReg); 461 for (int index = 16; index < 32; index++) { 462 uint32_t regVal = tc->readIntReg(index); 463 regVal = htog(regVal); 464 if (!tc->getMemProxy().tryWriteBlob( 465 sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 466 warn("Failed to save register to the stack when " 467 "flushing windows.\n"); 468 } 469 } 470 Canrestore--; 471 Cansave++; 472 CWP = (CWP + 1) % NWindows; 473 } 474 } 475 tc->setIntReg(NumIntArchRegs + 3, Cansave); 476 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 477 tc->setMiscReg(MISCREG_CWP, origCWP); 478} 479 480void 481Sparc64Process::flushWindows(ThreadContext *tc) 482{ 483 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 484 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 485 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 486 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 487 MiscReg origCWP = CWP; 488 CWP = (CWP + Cansave + 2) % NWindows; 489 while (NWindows - 2 - Cansave != 0) { 490 if (Otherwin) { 491 panic("Otherwin non-zero.\n"); 492 } else { 493 tc->setMiscReg(MISCREG_CWP, CWP); 494 // Do the stores 495 IntReg sp = tc->readIntReg(StackPointerReg); 496 for (int index = 16; index < 32; index++) { 497 IntReg regVal = tc->readIntReg(index); 498 regVal = htog(regVal); 499 if (!tc->getMemProxy().tryWriteBlob( 500 sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 501 warn("Failed to save register to the stack when " 502 "flushing windows.\n"); 503 } 504 } 505 Canrestore--; 506 Cansave++; 507 CWP = (CWP + 1) % NWindows; 508 } 509 } 510 tc->setIntReg(NumIntArchRegs + 3, Cansave); 511 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 512 tc->setMiscReg(MISCREG_CWP, origCWP); 513} 514 515IntReg 516Sparc32Process::getSyscallArg(ThreadContext *tc, int &i) 517{ 518 assert(i < 6); 519 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 520} 521 522void 523Sparc32Process::setSyscallArg(ThreadContext *tc, int i, IntReg val) 524{ 525 assert(i < 6); 526 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 527} 528 529IntReg 530Sparc64Process::getSyscallArg(ThreadContext *tc, int &i) 531{ 532 assert(i < 6); 533 return tc->readIntReg(FirstArgumentReg + i++); 534} 535 536void 537Sparc64Process::setSyscallArg(ThreadContext *tc, int i, IntReg val) 538{ 539 assert(i < 6); 540 tc->setIntReg(FirstArgumentReg + i, val); 541} 542 543void 544SparcProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 545{ 546 // check for error condition. SPARC syscall convention is to 547 // indicate success/failure in reg the carry bit of the ccr 548 // and put the return value itself in the standard return value reg (). 549 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 550 if (sysret.successful()) { 551 // no error, clear XCC.C 552 tc->setIntReg(NumIntArchRegs + 2, 553 tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 554 IntReg val = sysret.returnValue(); 555 if (pstate.am) 556 val = bits(val, 31, 0); 557 tc->setIntReg(ReturnValueReg, val); 558 } else { 559 // got an error, set XCC.C 560 tc->setIntReg(NumIntArchRegs + 2, 561 tc->readIntReg(NumIntArchRegs + 2) | 0x11); 562 IntReg val = sysret.errnoValue(); 563 if (pstate.am) 564 val = bits(val, 31, 0); 565 tc->setIntReg(ReturnValueReg, val); 566 } 567} 568