process.cc revision 11886
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 3211793Sbrandon.potter@amd.com#include "arch/sparc/process.hh" 3311793Sbrandon.potter@amd.com 343589Sgblack@eecs.umich.edu#include "arch/sparc/asi.hh" 354111Sgblack@eecs.umich.edu#include "arch/sparc/handlers.hh" 362474SN/A#include "arch/sparc/isa_traits.hh" 376335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 383760Sgblack@eecs.umich.edu#include "arch/sparc/types.hh" 398229Snate@binkert.org#include "base/loader/elf_object.hh" 402454SN/A#include "base/loader/object_file.hh" 412454SN/A#include "base/misc.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 438232Snate@binkert.org#include "debug/Stack.hh" 442561SN/A#include "mem/page_table.hh" 4511854Sbrandon.potter@amd.com#include "sim/aux_vector.hh" 464434Ssaidi@eecs.umich.edu#include "sim/process_impl.hh" 4711800Sbrandon.potter@amd.com#include "sim/syscall_return.hh" 482474SN/A#include "sim/system.hh" 492207SN/A 502458SN/Ausing namespace std; 512474SN/Ausing namespace SparcISA; 522458SN/A 535958Sgblack@eecs.umich.edustatic const int FirstArgumentReg = 8; 545958Sgblack@eecs.umich.edu 552207SN/A 5611851Sbrandon.potter@amd.comSparcProcess::SparcProcess(ProcessParams * params, ObjectFile *objFile, 5711851Sbrandon.potter@amd.com Addr _StackBias) 5811851Sbrandon.potter@amd.com : Process(params, objFile), StackBias(_StackBias) 592474SN/A{ 602474SN/A 612474SN/A // XXX all the below need to be updated for SPARC - Ali 6211886Sbrandon.potter@amd.com memState->brkPoint = objFile->dataBase() + objFile->dataSize() + 6311886Sbrandon.potter@amd.com objFile->bssSize(); 6411886Sbrandon.potter@amd.com memState->brkPoint = roundUp(memState->brkPoint, PageBytes); 652474SN/A 662474SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 6711886Sbrandon.potter@amd.com memState->nextThreadStackBase = memState->stackBase - (8 * 1024 * 1024); 683415Sgblack@eecs.umich.edu 697741Sgblack@eecs.umich.edu // Initialize these to 0s 703415Sgblack@eecs.umich.edu fillStart = 0; 713415Sgblack@eecs.umich.edu spillStart = 0; 722474SN/A} 732474SN/A 747741Sgblack@eecs.umich.eduvoid 7511877Sbrandon.potter@amd.comSparcProcess::handleTrap(int trapNum, ThreadContext *tc, Fault *fault) 764111Sgblack@eecs.umich.edu{ 777720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 787741Sgblack@eecs.umich.edu switch (trapNum) { 797741Sgblack@eecs.umich.edu case 0x01: // Software breakpoint 807720Sgblack@eecs.umich.edu warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 815128Sgblack@eecs.umich.edu break; 827741Sgblack@eecs.umich.edu case 0x02: // Division by zero 837720Sgblack@eecs.umich.edu warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 845128Sgblack@eecs.umich.edu break; 857741Sgblack@eecs.umich.edu case 0x03: // Flush window trap 865128Sgblack@eecs.umich.edu flushWindows(tc); 875128Sgblack@eecs.umich.edu break; 887741Sgblack@eecs.umich.edu case 0x04: // Clean windows 895128Sgblack@eecs.umich.edu warn("Ignoring process request for clean register " 907720Sgblack@eecs.umich.edu "windows at pc %#x.\n", pc.pc()); 915128Sgblack@eecs.umich.edu break; 927741Sgblack@eecs.umich.edu case 0x05: // Range check 937720Sgblack@eecs.umich.edu warn("Software signaled a range check at pc %#x.\n", pc.pc()); 945128Sgblack@eecs.umich.edu break; 957741Sgblack@eecs.umich.edu case 0x06: // Fix alignment 965128Sgblack@eecs.umich.edu warn("Ignoring process request for os assisted unaligned accesses " 977720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 985128Sgblack@eecs.umich.edu break; 997741Sgblack@eecs.umich.edu case 0x07: // Integer overflow 1007720Sgblack@eecs.umich.edu warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 1015128Sgblack@eecs.umich.edu break; 1027741Sgblack@eecs.umich.edu case 0x32: // Get integer condition codes 1035128Sgblack@eecs.umich.edu warn("Ignoring process request to get the integer condition codes " 1047720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 1055128Sgblack@eecs.umich.edu break; 1067741Sgblack@eecs.umich.edu case 0x33: // Set integer condition codes 1075128Sgblack@eecs.umich.edu warn("Ignoring process request to set the integer condition codes " 1087720Sgblack@eecs.umich.edu "at pc %#x.\n", pc.pc()); 1094111Sgblack@eecs.umich.edu break; 1104111Sgblack@eecs.umich.edu default: 1114111Sgblack@eecs.umich.edu panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 1124111Sgblack@eecs.umich.edu } 1134111Sgblack@eecs.umich.edu} 1144111Sgblack@eecs.umich.edu 1152474SN/Avoid 11611851Sbrandon.potter@amd.comSparcProcess::initState() 1174111Sgblack@eecs.umich.edu{ 11811851Sbrandon.potter@amd.com Process::initState(); 1194111Sgblack@eecs.umich.edu 1205713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1217741Sgblack@eecs.umich.edu // From the SPARC ABI 1224111Sgblack@eecs.umich.edu 1237741Sgblack@eecs.umich.edu // Setup default FP state 1245713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_FSR, 0); 1252646Ssaidi@eecs.umich.edu 1265713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TICK, 0); 1274997Sgblack@eecs.umich.edu 1282561SN/A /* 1292561SN/A * Register window management registers 1302561SN/A */ 1312561SN/A 1327741Sgblack@eecs.umich.edu // No windows contain info from other programs 1337741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); 1345713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 6, 0); 1357741Sgblack@eecs.umich.edu // There are no windows to pop 1367741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); 1375713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, 0); 1387741Sgblack@eecs.umich.edu // All windows are available to save into 1397741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); 1405713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, NWindows - 2); 1417741Sgblack@eecs.umich.edu // All windows are "clean" 1427741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); 1435713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 5, NWindows); 1447741Sgblack@eecs.umich.edu // Start with register window 0 1456337Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, 0); 1467741Sgblack@eecs.umich.edu // Always use spill and fill traps 0 1477741Sgblack@eecs.umich.edu // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); 1485713Shsul@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 7, 0); 1497741Sgblack@eecs.umich.edu // Set the trap level to 0 1505713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TL, 0); 1517741Sgblack@eecs.umich.edu // Set the ASI register to something fixed 1529375Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 1534997Sgblack@eecs.umich.edu 15411850Sbrandon.potter@amd.com // Set the MMU Primary Context Register to hold the process' pid 15511850Sbrandon.potter@amd.com tc->setMiscReg(MISCREG_MMU_P_CONTEXT, _pid); 15611850Sbrandon.potter@amd.com 1574997Sgblack@eecs.umich.edu /* 1584997Sgblack@eecs.umich.edu * T1 specific registers 1594997Sgblack@eecs.umich.edu */ 1607741Sgblack@eecs.umich.edu // Turn on the icache, dcache, dtb translation, and itb translation. 1615713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 1622474SN/A} 1632474SN/A 1645285Sgblack@eecs.umich.eduvoid 16511851Sbrandon.potter@amd.comSparc32Process::initState() 1662585SN/A{ 16711851Sbrandon.potter@amd.com SparcProcess::initState(); 1685285Sgblack@eecs.umich.edu 1695713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1707741Sgblack@eecs.umich.edu // The process runs in user mode with 32 bit addresses 1718829Sgblack@eecs.umich.edu PSTATE pstate = 0; 1728829Sgblack@eecs.umich.edu pstate.ie = 1; 1738829Sgblack@eecs.umich.edu pstate.am = 1; 1748829Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, pstate); 1755285Sgblack@eecs.umich.edu 17610318Sandreas.hansson@arm.com argsInit(32 / 8, PageBytes); 1774111Sgblack@eecs.umich.edu} 1783415Sgblack@eecs.umich.edu 1792561SN/Avoid 18011851Sbrandon.potter@amd.comSparc64Process::initState() 1812561SN/A{ 18211851Sbrandon.potter@amd.com SparcProcess::initState(); 1835285Sgblack@eecs.umich.edu 1845713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1857741Sgblack@eecs.umich.edu // The process runs in user mode 1868829Sgblack@eecs.umich.edu PSTATE pstate = 0; 1878829Sgblack@eecs.umich.edu pstate.ie = 1; 1888829Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PSTATE, pstate); 1895285Sgblack@eecs.umich.edu 19010318Sandreas.hansson@arm.com argsInit(sizeof(IntReg), PageBytes); 1915285Sgblack@eecs.umich.edu} 1925285Sgblack@eecs.umich.edu 1935285Sgblack@eecs.umich.edutemplate<class IntType> 1945285Sgblack@eecs.umich.eduvoid 19511851Sbrandon.potter@amd.comSparcProcess::argsInit(int pageSize) 1965285Sgblack@eecs.umich.edu{ 1975285Sgblack@eecs.umich.edu int intSize = sizeof(IntType); 1985285Sgblack@eecs.umich.edu 1995771Shsul@eecs.umich.edu typedef AuxVector<IntType> auxv_t; 2005285Sgblack@eecs.umich.edu 2015285Sgblack@eecs.umich.edu std::vector<auxv_t> auxv; 2022474SN/A 2033044Sgblack@eecs.umich.edu string filename; 2047741Sgblack@eecs.umich.edu if (argv.size() < 1) 2053044Sgblack@eecs.umich.edu filename = ""; 2063044Sgblack@eecs.umich.edu else 2073044Sgblack@eecs.umich.edu filename = argv[0]; 2083044Sgblack@eecs.umich.edu 2097741Sgblack@eecs.umich.edu // Even for a 32 bit process, the ABI says we still need to 2107741Sgblack@eecs.umich.edu // maintain double word alignment of the stack pointer. 2115286Sgblack@eecs.umich.edu uint64_t align = 16; 2122561SN/A 21311389Sbrandon.potter@amd.com // Patch the ld_bias for dynamic executables. 21411389Sbrandon.potter@amd.com updateBias(); 21511389Sbrandon.potter@amd.com 2162561SN/A // load object file into target memory 2172561SN/A objFile->loadSections(initVirtMem); 2182561SN/A 2192585SN/A enum hardwareCaps 2202585SN/A { 2212585SN/A M5_HWCAP_SPARC_FLUSH = 1, 2222585SN/A M5_HWCAP_SPARC_STBAR = 2, 2232585SN/A M5_HWCAP_SPARC_SWAP = 4, 2242585SN/A M5_HWCAP_SPARC_MULDIV = 8, 2252585SN/A M5_HWCAP_SPARC_V9 = 16, 2267741Sgblack@eecs.umich.edu // This one should technically only be set 2277741Sgblack@eecs.umich.edu // if there is a cheetah or cheetah_plus tlb, 2287741Sgblack@eecs.umich.edu // but we'll use it all the time 2292585SN/A M5_HWCAP_SPARC_ULTRA3 = 32 2302585SN/A }; 2312585SN/A 2322585SN/A const int64_t hwcap = 2332585SN/A M5_HWCAP_SPARC_FLUSH | 2342585SN/A M5_HWCAP_SPARC_STBAR | 2352585SN/A M5_HWCAP_SPARC_SWAP | 2362585SN/A M5_HWCAP_SPARC_MULDIV | 2372585SN/A M5_HWCAP_SPARC_V9 | 2382585SN/A M5_HWCAP_SPARC_ULTRA3; 2392585SN/A 2407741Sgblack@eecs.umich.edu // Setup the auxilliary vectors. These will already have endian conversion. 2417741Sgblack@eecs.umich.edu // Auxilliary vectors are loaded only for elf formatted executables. 2422976Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 2437741Sgblack@eecs.umich.edu if (elfObject) { 2447741Sgblack@eecs.umich.edu // Bits which describe the system hardware capabilities 2454793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap)); 2467741Sgblack@eecs.umich.edu // The system page size 24710318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::PageBytes)); 2487741Sgblack@eecs.umich.edu // Defined to be 100 in the kernel source. 2497741Sgblack@eecs.umich.edu // Frequency at which times() increments 2504793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 2512976Sgblack@eecs.umich.edu // For statically linked executables, this is the virtual address of the 2522976Sgblack@eecs.umich.edu // program header tables if they appear in the executable image 2534793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 2542976Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 2554793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 2562976Sgblack@eecs.umich.edu // This is the number of program headers from the original elf file. 2574793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 25811389Sbrandon.potter@amd.com // This is the base address of the ELF interpreter; it should be 25911389Sbrandon.potter@amd.com // zero for static executables or contain the base address for 26011389Sbrandon.potter@amd.com // dynamic executables. 26111389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 2627741Sgblack@eecs.umich.edu // This is hardwired to 0 in the elf loading code in the kernel 2634793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 2647741Sgblack@eecs.umich.edu // The entry point to the program 2654793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 2667741Sgblack@eecs.umich.edu // Different user and group IDs 2674793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 2684793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 2694793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 2704793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 2717741Sgblack@eecs.umich.edu // Whether to enable "secure mode" in the executable 2724793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 2732976Sgblack@eecs.umich.edu } 2742585SN/A 2757741Sgblack@eecs.umich.edu // Figure out how big the initial stack needs to be 2762561SN/A 2774164Sgblack@eecs.umich.edu // The unaccounted for 8 byte 0 at the top of the stack 2785286Sgblack@eecs.umich.edu int sentry_size = 8; 2794111Sgblack@eecs.umich.edu 2807741Sgblack@eecs.umich.edu // This is the name of the file which is present on the initial stack 2817741Sgblack@eecs.umich.edu // It's purpose is to let the user space linker examine the original file. 2824111Sgblack@eecs.umich.edu int file_name_size = filename.size() + 1; 2834111Sgblack@eecs.umich.edu 2844111Sgblack@eecs.umich.edu int env_data_size = 0; 2854111Sgblack@eecs.umich.edu for (int i = 0; i < envp.size(); ++i) { 2864111Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 2874111Sgblack@eecs.umich.edu } 2884111Sgblack@eecs.umich.edu int arg_data_size = 0; 2894111Sgblack@eecs.umich.edu for (int i = 0; i < argv.size(); ++i) { 2904111Sgblack@eecs.umich.edu arg_data_size += argv[i].size() + 1; 2914111Sgblack@eecs.umich.edu } 2924111Sgblack@eecs.umich.edu 2937741Sgblack@eecs.umich.edu // The info_block. 2945286Sgblack@eecs.umich.edu int base_info_block_size = 2955286Sgblack@eecs.umich.edu sentry_size + file_name_size + env_data_size + arg_data_size; 2965286Sgblack@eecs.umich.edu 2975286Sgblack@eecs.umich.edu int info_block_size = roundUp(base_info_block_size, align); 2985286Sgblack@eecs.umich.edu 2995286Sgblack@eecs.umich.edu int info_block_padding = info_block_size - base_info_block_size; 3004111Sgblack@eecs.umich.edu 3017741Sgblack@eecs.umich.edu // Each auxilliary vector is two words 3024111Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 3034111Sgblack@eecs.umich.edu 3044111Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 3054111Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 3064111Sgblack@eecs.umich.edu 3074111Sgblack@eecs.umich.edu int argc_size = intSize; 3084111Sgblack@eecs.umich.edu int window_save_size = intSize * 16; 3094111Sgblack@eecs.umich.edu 3107741Sgblack@eecs.umich.edu // Figure out the size of the contents of the actual initial frame 3115286Sgblack@eecs.umich.edu int frame_size = 3124111Sgblack@eecs.umich.edu aux_array_size + 3134111Sgblack@eecs.umich.edu envp_array_size + 3144111Sgblack@eecs.umich.edu argv_array_size + 3154111Sgblack@eecs.umich.edu argc_size + 3164111Sgblack@eecs.umich.edu window_save_size; 3174111Sgblack@eecs.umich.edu 3187741Sgblack@eecs.umich.edu // There needs to be padding after the auxiliary vector data so that the 3197741Sgblack@eecs.umich.edu // very bottom of the stack is aligned properly. 3205286Sgblack@eecs.umich.edu int aligned_partial_size = roundUp(frame_size, align); 3215286Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - frame_size; 3225286Sgblack@eecs.umich.edu 3235286Sgblack@eecs.umich.edu int space_needed = 3245286Sgblack@eecs.umich.edu info_block_size + 3255286Sgblack@eecs.umich.edu aux_padding + 3265286Sgblack@eecs.umich.edu frame_size; 3275286Sgblack@eecs.umich.edu 32811886Sbrandon.potter@amd.com memState->stackMin = memState->stackBase - space_needed; 32911886Sbrandon.potter@amd.com memState->stackMin = roundDown(memState->stackMin, align); 33011886Sbrandon.potter@amd.com memState->stackSize = memState->stackBase - memState->stackMin; 3314111Sgblack@eecs.umich.edu 3325285Sgblack@eecs.umich.edu // Allocate space for the stack 33311886Sbrandon.potter@amd.com allocateMem(roundDown(memState->stackMin, pageSize), 33411886Sbrandon.potter@amd.com roundUp(memState->stackSize, pageSize)); 3354111Sgblack@eecs.umich.edu 3364111Sgblack@eecs.umich.edu // map out initial stack contents 33711886Sbrandon.potter@amd.com IntType sentry_base = memState->stackBase - sentry_size; 3385286Sgblack@eecs.umich.edu IntType file_name_base = sentry_base - file_name_size; 3395286Sgblack@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 3405286Sgblack@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 3415286Sgblack@eecs.umich.edu IntType auxv_array_base = arg_data_base - 3425286Sgblack@eecs.umich.edu info_block_padding - aux_array_size - aux_padding; 3435286Sgblack@eecs.umich.edu IntType envp_array_base = auxv_array_base - envp_array_size; 3445286Sgblack@eecs.umich.edu IntType argv_array_base = envp_array_base - argv_array_size; 3455286Sgblack@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 3465286Sgblack@eecs.umich.edu#if TRACING_ON 3475286Sgblack@eecs.umich.edu IntType window_save_base = argc_base - window_save_size; 3485286Sgblack@eecs.umich.edu#endif 3494111Sgblack@eecs.umich.edu 3505941Sgblack@eecs.umich.edu DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 3515941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 3525941Sgblack@eecs.umich.edu DPRINTF(Stack, "filename = %s\n", filename); 3535941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - file name\n", file_name_base); 3545941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - env data\n", env_data_base); 3555941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 3565941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 3575941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 3585941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 3595941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - argc \n", argc_base); 3605941Sgblack@eecs.umich.edu DPRINTF(Stack, "%#x - window save\n", window_save_base); 36111886Sbrandon.potter@amd.com DPRINTF(Stack, "%#x - stack min\n", memState->stackMin); 3624111Sgblack@eecs.umich.edu 36311886Sbrandon.potter@amd.com assert(window_save_base == memState->stackMin); 3645286Sgblack@eecs.umich.edu 3654111Sgblack@eecs.umich.edu // write contents to stack 3664111Sgblack@eecs.umich.edu 3674111Sgblack@eecs.umich.edu // figure out argc 3685285Sgblack@eecs.umich.edu IntType argc = argv.size(); 3695567Snate@binkert.org IntType guestArgc = SparcISA::htog(argc); 3704111Sgblack@eecs.umich.edu 3717741Sgblack@eecs.umich.edu // Write out the sentry void * 3725286Sgblack@eecs.umich.edu uint64_t sentry_NULL = 0; 3738852Sandreas.hansson@arm.com initVirtMem.writeBlob(sentry_base, 3745286Sgblack@eecs.umich.edu (uint8_t*)&sentry_NULL, sentry_size); 3754111Sgblack@eecs.umich.edu 3767741Sgblack@eecs.umich.edu // Write the file name 3778852Sandreas.hansson@arm.com initVirtMem.writeString(file_name_base, filename.c_str()); 3784111Sgblack@eecs.umich.edu 3797741Sgblack@eecs.umich.edu // Copy the aux stuff 3807741Sgblack@eecs.umich.edu for (int x = 0; x < auxv.size(); x++) { 3818852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 3824111Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 3838852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 3844111Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 3854111Sgblack@eecs.umich.edu } 3865285Sgblack@eecs.umich.edu 3877741Sgblack@eecs.umich.edu // Write out the terminating zeroed auxilliary vector 3885285Sgblack@eecs.umich.edu const IntType zero = 0; 3898852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 3905286Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3918852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 3925286Sgblack@eecs.umich.edu (uint8_t*)&zero, intSize); 3934111Sgblack@eecs.umich.edu 3944117Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 3954117Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 3964111Sgblack@eecs.umich.edu 3978852Sandreas.hansson@arm.com initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 3984111Sgblack@eecs.umich.edu 3997741Sgblack@eecs.umich.edu // Set up space for the trap handlers into the processes address space. 4007741Sgblack@eecs.umich.edu // Since the stack grows down and there is reserved address space abov 4017741Sgblack@eecs.umich.edu // it, we can put stuff above it and stay out of the way. 40211886Sbrandon.potter@amd.com fillStart = memState->stackBase; 4035285Sgblack@eecs.umich.edu spillStart = fillStart + sizeof(MachInst) * numFillInsts; 4044111Sgblack@eecs.umich.edu 4055713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 4067741Sgblack@eecs.umich.edu // Set up the thread context to start running the process 4077741Sgblack@eecs.umich.edu // assert(NumArgumentRegs >= 2); 4087741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[0], argc); 4097741Sgblack@eecs.umich.edu // tc->setIntReg(ArgumentReg[1], argv_array_base); 41011886Sbrandon.potter@amd.com tc->setIntReg(StackPointerReg, memState->stackMin - StackBias); 4114111Sgblack@eecs.umich.edu 4125231Sgblack@eecs.umich.edu // %g1 is a pointer to a function that should be run at exit. Since we 4135231Sgblack@eecs.umich.edu // don't have anything like that, it should be set to 0. 4145713Shsul@eecs.umich.edu tc->setIntReg(1, 0); 4155231Sgblack@eecs.umich.edu 41611389Sbrandon.potter@amd.com tc->pcState(getStartPC()); 4174111Sgblack@eecs.umich.edu 4187741Sgblack@eecs.umich.edu // Align the "stack_min" to a page boundary. 41911886Sbrandon.potter@amd.com memState->stackMin = roundDown(memState->stackMin, pageSize); 4204111Sgblack@eecs.umich.edu} 4215128Sgblack@eecs.umich.edu 4225285Sgblack@eecs.umich.eduvoid 42311851Sbrandon.potter@amd.comSparc64Process::argsInit(int intSize, int pageSize) 4245285Sgblack@eecs.umich.edu{ 42511851Sbrandon.potter@amd.com SparcProcess::argsInit<uint64_t>(pageSize); 4265285Sgblack@eecs.umich.edu 4275285Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4288852Sandreas.hansson@arm.com initVirtMem.writeBlob(fillStart, 4295285Sgblack@eecs.umich.edu (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 4308852Sandreas.hansson@arm.com initVirtMem.writeBlob(spillStart, 4315285Sgblack@eecs.umich.edu (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 4325285Sgblack@eecs.umich.edu} 4335285Sgblack@eecs.umich.edu 4345285Sgblack@eecs.umich.eduvoid 43511851Sbrandon.potter@amd.comSparc32Process::argsInit(int intSize, int pageSize) 4365285Sgblack@eecs.umich.edu{ 43711851Sbrandon.potter@amd.com SparcProcess::argsInit<uint32_t>(pageSize); 4385285Sgblack@eecs.umich.edu 4395285Sgblack@eecs.umich.edu // Stuff the trap handlers into the process address space 4408852Sandreas.hansson@arm.com initVirtMem.writeBlob(fillStart, 4415285Sgblack@eecs.umich.edu (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 4428852Sandreas.hansson@arm.com initVirtMem.writeBlob(spillStart, 4435285Sgblack@eecs.umich.edu (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 4445285Sgblack@eecs.umich.edu} 4455285Sgblack@eecs.umich.edu 44611851Sbrandon.potter@amd.comvoid Sparc32Process::flushWindows(ThreadContext *tc) 4475128Sgblack@eecs.umich.edu{ 4485128Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4495128Sgblack@eecs.umich.edu IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4505128Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4515128Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4525128Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 4535128Sgblack@eecs.umich.edu CWP = (CWP + Cansave + 2) % NWindows; 4547741Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4555128Sgblack@eecs.umich.edu if (Otherwin) { 4565128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4575128Sgblack@eecs.umich.edu } else { 4585128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4597741Sgblack@eecs.umich.edu // Do the stores 4605128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4615128Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4625287Sgblack@eecs.umich.edu uint32_t regVal = tc->readIntReg(index); 4635128Sgblack@eecs.umich.edu regVal = htog(regVal); 4648852Sandreas.hansson@arm.com if (!tc->getMemProxy().tryWriteBlob( 4655128Sgblack@eecs.umich.edu sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 4665128Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 4675128Sgblack@eecs.umich.edu "flushing windows.\n"); 4685128Sgblack@eecs.umich.edu } 4695128Sgblack@eecs.umich.edu } 4705128Sgblack@eecs.umich.edu Canrestore--; 4715128Sgblack@eecs.umich.edu Cansave++; 4725128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 4735128Sgblack@eecs.umich.edu } 4745128Sgblack@eecs.umich.edu } 4755128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 4765128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 4775128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 4785128Sgblack@eecs.umich.edu} 4795128Sgblack@eecs.umich.edu 4807741Sgblack@eecs.umich.eduvoid 48111851Sbrandon.potter@amd.comSparc64Process::flushWindows(ThreadContext *tc) 4825128Sgblack@eecs.umich.edu{ 4835128Sgblack@eecs.umich.edu IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 4845128Sgblack@eecs.umich.edu IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 4855128Sgblack@eecs.umich.edu IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 4865128Sgblack@eecs.umich.edu MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 4875128Sgblack@eecs.umich.edu MiscReg origCWP = CWP; 4885128Sgblack@eecs.umich.edu CWP = (CWP + Cansave + 2) % NWindows; 4897741Sgblack@eecs.umich.edu while (NWindows - 2 - Cansave != 0) { 4905128Sgblack@eecs.umich.edu if (Otherwin) { 4915128Sgblack@eecs.umich.edu panic("Otherwin non-zero.\n"); 4925128Sgblack@eecs.umich.edu } else { 4935128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, CWP); 4947741Sgblack@eecs.umich.edu // Do the stores 4955128Sgblack@eecs.umich.edu IntReg sp = tc->readIntReg(StackPointerReg); 4965128Sgblack@eecs.umich.edu for (int index = 16; index < 32; index++) { 4975128Sgblack@eecs.umich.edu IntReg regVal = tc->readIntReg(index); 4985128Sgblack@eecs.umich.edu regVal = htog(regVal); 4998852Sandreas.hansson@arm.com if (!tc->getMemProxy().tryWriteBlob( 5005128Sgblack@eecs.umich.edu sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 5015128Sgblack@eecs.umich.edu warn("Failed to save register to the stack when " 5025128Sgblack@eecs.umich.edu "flushing windows.\n"); 5035128Sgblack@eecs.umich.edu } 5045128Sgblack@eecs.umich.edu } 5055128Sgblack@eecs.umich.edu Canrestore--; 5065128Sgblack@eecs.umich.edu Cansave++; 5075128Sgblack@eecs.umich.edu CWP = (CWP + 1) % NWindows; 5085128Sgblack@eecs.umich.edu } 5095128Sgblack@eecs.umich.edu } 5105128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 3, Cansave); 5115128Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 4, Canrestore); 5125128Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CWP, origCWP); 5135128Sgblack@eecs.umich.edu} 5145958Sgblack@eecs.umich.edu 5155958Sgblack@eecs.umich.eduIntReg 51611851Sbrandon.potter@amd.comSparc32Process::getSyscallArg(ThreadContext *tc, int &i) 5175958Sgblack@eecs.umich.edu{ 5185958Sgblack@eecs.umich.edu assert(i < 6); 5196701Sgblack@eecs.umich.edu return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 5205958Sgblack@eecs.umich.edu} 5215958Sgblack@eecs.umich.edu 5225958Sgblack@eecs.umich.eduvoid 52311851Sbrandon.potter@amd.comSparc32Process::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5245958Sgblack@eecs.umich.edu{ 5255958Sgblack@eecs.umich.edu assert(i < 6); 5265958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 5275958Sgblack@eecs.umich.edu} 5285958Sgblack@eecs.umich.edu 5295958Sgblack@eecs.umich.eduIntReg 53011851Sbrandon.potter@amd.comSparc64Process::getSyscallArg(ThreadContext *tc, int &i) 5315958Sgblack@eecs.umich.edu{ 5325958Sgblack@eecs.umich.edu assert(i < 6); 5336701Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i++); 5345958Sgblack@eecs.umich.edu} 5355958Sgblack@eecs.umich.edu 5365958Sgblack@eecs.umich.eduvoid 53711851Sbrandon.potter@amd.comSparc64Process::setSyscallArg(ThreadContext *tc, int i, IntReg val) 5385958Sgblack@eecs.umich.edu{ 5395958Sgblack@eecs.umich.edu assert(i < 6); 5405958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 5415958Sgblack@eecs.umich.edu} 5425958Sgblack@eecs.umich.edu 5435958Sgblack@eecs.umich.eduvoid 54411851Sbrandon.potter@amd.comSparcProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 5455958Sgblack@eecs.umich.edu{ 5465958Sgblack@eecs.umich.edu // check for error condition. SPARC syscall convention is to 5475958Sgblack@eecs.umich.edu // indicate success/failure in reg the carry bit of the ccr 5485958Sgblack@eecs.umich.edu // and put the return value itself in the standard return value reg (). 5498829Sgblack@eecs.umich.edu PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 55010223Ssteve.reinhardt@amd.com if (sysret.successful()) { 5515958Sgblack@eecs.umich.edu // no error, clear XCC.C 5525958Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 2, 55310223Ssteve.reinhardt@amd.com tc->readIntReg(NumIntArchRegs + 2) & 0xEE); 55410223Ssteve.reinhardt@amd.com IntReg val = sysret.returnValue(); 5558829Sgblack@eecs.umich.edu if (pstate.am) 5565958Sgblack@eecs.umich.edu val = bits(val, 31, 0); 5575958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5585958Sgblack@eecs.umich.edu } else { 5595958Sgblack@eecs.umich.edu // got an error, set XCC.C 5605958Sgblack@eecs.umich.edu tc->setIntReg(NumIntArchRegs + 2, 56110223Ssteve.reinhardt@amd.com tc->readIntReg(NumIntArchRegs + 2) | 0x11); 56210223Ssteve.reinhardt@amd.com IntReg val = sysret.errnoValue(); 5638829Sgblack@eecs.umich.edu if (pstate.am) 5645958Sgblack@eecs.umich.edu val = bits(val, 31, 0); 5655958Sgblack@eecs.umich.edu tc->setIntReg(ReturnValueReg, val); 5665958Sgblack@eecs.umich.edu } 5675958Sgblack@eecs.umich.edu} 568