pagetable.hh revision 5555:07c10d7dd62d
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#ifndef __ARCH_SPARC_PAGETABLE_HH__ 32#define __ARCH_SPARC_PAGETABLE_HH__ 33 34#include "arch/sparc/isa_traits.hh" 35#include "base/bitfield.hh" 36#include "base/misc.hh" 37#include "config/full_system.hh" 38 39class Checkpoint; 40 41namespace SparcISA { 42 43struct VAddr 44{ 45 VAddr(Addr a) { panic("not implemented yet."); } 46}; 47 48class TteTag 49{ 50 private: 51 uint64_t entry; 52 bool populated; 53 54 public: 55 TteTag() : entry(0), populated(false) {} 56 TteTag(uint64_t e) : entry(e), populated(true) {} 57 58 const TteTag & 59 operator=(uint64_t e) 60 { 61 populated = true; 62 entry = e; 63 return *this; 64 } 65 66 bool valid() const {assert(populated); return !bits(entry,62,62); } 67 Addr va() const {assert(populated); return bits(entry,41,0); } 68}; 69 70 71class PageTableEntry 72{ 73 public: 74 enum EntryType { 75 sun4v, 76 sun4u, 77 invalid 78 }; 79 80 private: 81 uint64_t entry; 82 EntryType type; 83 uint64_t entry4u; 84 bool populated; 85 86 public: 87 PageTableEntry() 88 : entry(0), type(invalid), populated(false) 89 {} 90 91 PageTableEntry(uint64_t e, EntryType t = sun4u) 92 : entry(e), type(t), populated(true) 93 { 94 populate(entry, type); 95 } 96 97 void populate(uint64_t e, EntryType t = sun4u) 98 { 99 entry = e; 100 type = t; 101 populated = true; 102 103 // If we get a sun4v format TTE, turn it into a sun4u 104 if (type == sun4u) 105 entry4u = entry; 106 else { 107 entry4u = 0; 108 entry4u |= mbits(entry,63,63); //valid 109 entry4u |= bits(entry,1,0) << 61; //size[1:0] 110 entry4u |= bits(entry,62,62) << 60; //nfo 111 entry4u |= bits(entry,12,12) << 59; //ie 112 entry4u |= bits(entry,2,2) << 48; //size[2] 113 entry4u |= mbits(entry,39,13); //paddr 114 entry4u |= bits(entry,61,61) << 6;; // locked 115 entry4u |= bits(entry,10,10) << 5; //cp 116 entry4u |= bits(entry,9,9) << 4; //cv 117 entry4u |= bits(entry,11,11) << 3; //e 118 entry4u |= bits(entry,8,8) << 2; //p 119 entry4u |= bits(entry,6,6) << 1; //w 120 } 121 } 122 123 void 124 clear() 125 { 126 populated = false; 127 } 128 129 static int pageSizes[6]; 130 131 uint64_t operator()() const { assert(populated); return entry4u; } 132 const PageTableEntry & 133 operator=(uint64_t e) 134 { 135 populated = true; 136 entry4u = e; 137 return *this; 138 } 139 140 const PageTableEntry & 141 operator=(const PageTableEntry &e) 142 { 143 populated = true; 144 entry4u = e.entry4u; 145 type = e.type; 146 return *this; 147 } 148 149 bool valid() const { return bits(entry4u,63,63) && populated; } 150 151 uint8_t 152 _size() const 153 { 154 assert(populated); 155 return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2; 156 } 157 158 Addr size() const { assert(_size() < 6); return pageSizes[_size()]; } 159 Addr sizeMask() const { return size() - 1; } 160 bool ie() const { return bits(entry4u, 59,59); } 161 Addr pfn() const { assert(populated); return bits(entry4u,39,13); } 162 Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);} 163 bool locked() const { assert(populated); return bits(entry4u,6,6); } 164 bool cv() const { assert(populated); return bits(entry4u,4,4); } 165 bool cp() const { assert(populated); return bits(entry4u,5,5); } 166 bool priv() const { assert(populated); return bits(entry4u,2,2); } 167 bool writable() const { assert(populated); return bits(entry4u,1,1); } 168 bool nofault() const { assert(populated); return bits(entry4u,60,60); } 169 bool sideffect() const { assert(populated); return bits(entry4u,3,3); } 170 Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); } 171 172 Addr 173 translate(Addr vaddr) const 174 { 175 assert(populated); 176 Addr mask = sizeMask(); 177 return (paddr() & ~mask) | (vaddr & mask); 178 } 179}; 180 181struct TlbRange 182{ 183 Addr va; 184 Addr size; 185 int contextId; 186 int partitionId; 187 bool real; 188 189 inline bool 190 operator<(const TlbRange &r2) const 191 { 192 if (real && !r2.real) 193 return true; 194 if (!real && r2.real) 195 return false; 196 197 if (!real && !r2.real) { 198 if (contextId < r2.contextId) 199 return true; 200 else if (contextId > r2.contextId) 201 return false; 202 } 203 204 if (partitionId < r2.partitionId) 205 return true; 206 else if (partitionId > r2.partitionId) 207 return false; 208 209 if (va < r2.va) 210 return true; 211 return false; 212 } 213 214 inline bool 215 operator==(const TlbRange &r2) const 216 { 217 return va == r2.va && 218 size == r2.size && 219 contextId == r2.contextId && 220 partitionId == r2.partitionId && 221 real == r2.real; 222 } 223}; 224 225 226struct TlbEntry 227{ 228 TlbEntry() 229 {} 230 231 TlbEntry(Addr asn, Addr vaddr, Addr paddr) 232 { 233 uint64_t entry = 0; 234 entry |= 1ULL << 1; // Writable 235 entry |= 0ULL << 2; // Available in nonpriveleged mode 236 entry |= 0ULL << 3; // No side effects 237 entry |= 1ULL << 4; // Virtually cachable 238 entry |= 1ULL << 5; // Physically cachable 239 entry |= 0ULL << 6; // Not locked 240 entry |= mbits(paddr, 39, 13); // Physical address 241 entry |= 0ULL << 48; // size = 8k 242 entry |= 0uLL << 59; // Endianness not inverted 243 entry |= 0ULL << 60; // Not no fault only 244 entry |= 0ULL << 61; // size = 8k 245 entry |= 1ULL << 63; // valid 246 pte = PageTableEntry(entry); 247 248 range.va = vaddr; 249 range.size = 8*(1<<10); 250 range.contextId = asn; 251 range.partitionId = 0; 252 range.real = false; 253 254 valid = true; 255 } 256 257 TlbRange range; 258 PageTableEntry pte; 259 bool used; 260 bool valid; 261 262 Addr pageStart() 263 { 264 return pte.paddr(); 265 } 266 267 void serialize(std::ostream &os); 268 void unserialize(Checkpoint *cp, const std::string §ion); 269}; 270 271} // namespace SparcISA 272 273#endif // __ARCH_SPARC_PAGE_TABLE_HH__ 274 275