isa_traits.hh revision 8739:925f15f96322
12497SN/A/* 212780Snikos.nikoleris@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 38711SN/A * All rights reserved. 48711SN/A * 58711SN/A * Redistribution and use in source and binary forms, with or without 68711SN/A * modification, are permitted provided that the following conditions are 78711SN/A * met: redistributions of source code must retain the above copyright 88711SN/A * notice, this list of conditions and the following disclaimer; 98711SN/A * redistributions in binary form must reproduce the above copyright 108711SN/A * notice, this list of conditions and the following disclaimer in the 118711SN/A * documentation and/or other materials provided with the distribution; 128711SN/A * neither the name of the copyright holders nor the names of its 138711SN/A * contributors may be used to endorse or promote products derived from 142497SN/A * this software without specific prior written permission. 152497SN/A * 162497SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172497SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182497SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192497SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202497SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212497SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222497SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232497SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242497SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252497SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262497SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272497SN/A * 282497SN/A * Authors: Gabe Black 292497SN/A * Ali Saidi 302497SN/A */ 312497SN/A 322497SN/A#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 332497SN/A#define __ARCH_SPARC_ISA_TRAITS_HH__ 342497SN/A 352497SN/A#include "arch/sparc/sparc_traits.hh" 362497SN/A#include "arch/sparc/types.hh" 372497SN/A#include "base/types.hh" 382497SN/A#include "cpu/static_inst_fwd.hh" 392665SN/A 402665SN/Anamespace BigEndianGuest {} 418715SN/A 428922SN/Anamespace SparcISA 4312351Snikos.nikoleris@arm.com{ 442497SN/Aconst int MachineBytes = 8; 452497SN/A 462497SN/A// This makes sure the big endian versions of certain functions are used. 472982SN/Ausing namespace BigEndianGuest; 4810405Sandreas.hansson@arm.com 492497SN/A// SPARC has a delay slot 502497SN/A#define ISA_HAS_DELAY_SLOT 1 5111793Sbrandon.potter@amd.com 5211793Sbrandon.potter@amd.com// SPARC NOP (sethi %(hi(0), g0) 5312334Sgabeblack@google.comconst MachInst NoopMachInst = 0x01000000; 542548SN/A 5510405Sandreas.hansson@arm.com// 8K. This value is implmentation specific; and should probably 5610405Sandreas.hansson@arm.com// be somewhere else. 579524SN/Aconst int LogVMPageSize = 13; 582497SN/Aconst int VMPageSize = (1 << LogVMPageSize); 5910405Sandreas.hansson@arm.com 6010719SMarco.Balboni@ARM.com// real address virtual mapping 6111334Sandreas.hansson@arm.com// sort of like alpha super page, but less frequently used 6212341Snikos.nikoleris@arm.comconst Addr SegKPMEnd = ULL(0xfffffffc00000000); 6312341Snikos.nikoleris@arm.comconst Addr SegKPMBase = ULL(0xfffffac000000000); 647523SN/A 658851SN/A// Why does both the previous set of constants and this one exist? 668948SN/Aconst int PageShift = 13; 678948SN/Aconst int PageBytes = 1ULL << PageShift; 688851SN/A 699095SN/Aconst int BranchPredAddrShiftAmt = 2; 7010405Sandreas.hansson@arm.com 718922SN/AStaticInstPtr decodeInst(ExtMachInst); 729715SN/A 739715SN/A/////////// TLB Stuff //////////// 7410713Sandreas.hansson@arm.comconst Addr StartVAddrHole = ULL(0x0000800000000000); 7510713Sandreas.hansson@arm.comconst Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 768851SN/Aconst Addr VAddrAMask = ULL(0xFFFFFFFF); 778851SN/Aconst Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 788948SN/Aconst Addr BytesInPageMask = ULL(0x1FFF); 798948SN/A 808915SN/Aenum InterruptTypes 819031SN/A{ 829095SN/A IT_TRAP_LEVEL_ZERO, 8310405Sandreas.hansson@arm.com IT_HINTP, 849036SN/A IT_INT_VEC, 858922SN/A IT_CPU_MONDO, 869715SN/A IT_DEV_MONDO, 879715SN/A IT_RES_ERROR, 8810713Sandreas.hansson@arm.com IT_SOFT_INT, 8910713Sandreas.hansson@arm.com NumInterruptTypes 9010713Sandreas.hansson@arm.com}; 918915SN/A 928915SN/A// Memory accesses cannot be unaligned 938948SN/Aconst bool HasUnalignedMemAcc = false; 948851SN/A} 959095SN/A 9610888Sandreas.hansson@arm.com#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 978922SN/A