isa_traits.hh revision 6326:008930a4ace5
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 33#define __ARCH_SPARC_ISA_TRAITS_HH__ 34 35#include "arch/sparc/types.hh" 36#include "arch/sparc/max_inst_regs.hh" 37#include "arch/sparc/sparc_traits.hh" 38#include "base/types.hh" 39#include "config/full_system.hh" 40 41class StaticInstPtr; 42 43namespace BigEndianGuest {} 44 45namespace SparcISA 46{ 47 const int MachineBytes = 8; 48 49 //This makes sure the big endian versions of certain functions are used. 50 using namespace BigEndianGuest; 51 using SparcISAInst::MaxInstSrcRegs; 52 using SparcISAInst::MaxInstDestRegs; 53 54 // SPARC has a delay slot 55 #define ISA_HAS_DELAY_SLOT 1 56 57 // SPARC NOP (sethi %(hi(0), g0) 58 const MachInst NoopMachInst = 0x01000000; 59 60 // These enumerate all the registers for dependence tracking. 61 enum DependenceTags { 62 FP_Base_DepTag = 32*3+9, 63 Ctrl_Base_DepTag = FP_Base_DepTag + 64 64 }; 65 66 // semantically meaningful register indices 67 const int ZeroReg = 0; // architecturally meaningful 68 // the rest of these depend on the ABI 69 const int ReturnAddressReg = 31; // post call, precall is 15 70 const int ReturnValueReg = 8; // Post return, 24 is pre-return. 71 const int StackPointerReg = 14; 72 const int FramePointerReg = 30; 73 74 // Some OS syscall use a second register (o1) to return a second value 75 const int SyscallPseudoReturnReg = 9; 76 77 //8K. This value is implmentation specific; and should probably 78 //be somewhere else. 79 const int LogVMPageSize = 13; 80 const int VMPageSize = (1 << LogVMPageSize); 81 82 // real address virtual mapping 83 // sort of like alpha super page, but less frequently used 84 const Addr SegKPMEnd = ULL(0xfffffffc00000000); 85 const Addr SegKPMBase = ULL(0xfffffac000000000); 86 87 //Why does both the previous set of constants and this one exist? 88 const int PageShift = 13; 89 const int PageBytes = 1ULL << PageShift; 90 91 const int BranchPredAddrShiftAmt = 2; 92 93 StaticInstPtr decodeInst(ExtMachInst); 94 95 /////////// TLB Stuff //////////// 96 const Addr StartVAddrHole = ULL(0x0000800000000000); 97 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 98 const Addr VAddrAMask = ULL(0xFFFFFFFF); 99 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 100 const Addr BytesInPageMask = ULL(0x1FFF); 101 102#if FULL_SYSTEM 103 // I don't know what it's for, so I don't 104 // know what SPARC's value should be 105 // For loading... XXX This maybe could be USegEnd?? --ali 106 const Addr LoadAddrMask = ULL(0xffffffffff); 107 108 enum InterruptTypes 109 { 110 IT_TRAP_LEVEL_ZERO, 111 IT_HINTP, 112 IT_INT_VEC, 113 IT_CPU_MONDO, 114 IT_DEV_MONDO, 115 IT_RES_ERROR, 116 IT_SOFT_INT, 117 NumInterruptTypes 118 }; 119 120#endif 121} 122 123#endif // __ARCH_SPARC_ISA_TRAITS_HH__ 124